COSMAC 1802 CPUs, speed & voltage tests

Last updated Oct 31 2019 boo!. Edited by Herb Johnson.


This is a document about tests of various 1802-class CPU chips, at various voltages for Vcc and Vdd, and various clock speeds and instructions. The first set of tests were designed and performed by Ian May, during May 2017 and July 2017. He reported and discussed his results in Yahoo group cosmacelf, on YouTube, and in private conversations with me. These are summarized and edited here, with permission. I also have copies of Ian's tests results, linked to this document. The second set of tests were by Denny Rugenstein in Oct 2019 and posted in the same group (at; the results are as-posted. - Herb

Ian May's tests 2017

Ian May posted his first results during May 2017, on Yahoo discussion group "cosmacelf". Tests were posted as "Challenge: 1802AE vs 1802 ACE - which is which?" in cosmacelf Yahoo, May 27 2017 by Ian May. Additional testing results, were sent to me July 16 to 21st. Photos of his test circuits were provided during Aug 2017. Technical Comments near the end of this document have discussion of some details.

YouTube Videos: Ian made some videos high-speed operation of his EElf circuit, uncooled and cooled.and posted them to YouTube, July 27 2017, with updates. Details on the videos and links, follow the test results below.

Ian reviewed this summary and notes, provided more information and details and commentary. My thanks to Ian for his good and detailed work, and patiently sharing his work with me in this fashion.

Denny Rugenstein tests 2019

Denny Rugenstein posted his result in Oct 28 and 30 at the successor cosmacelf discussion group at He tested the Lee Hart 1802 Membership Card model K2 CPU board and front panel board, with different external clock rates and at different DC power voltages for the whole board-set; to determine the maximum clock rate at minimum DC voltage. Thanks to Denny for permission to share his work here.

Other power, current, frequency tests

Additional 1802 tests are listed on this linked Web page. - Herb

Ian May, Tests of May and July 2017

Descriptions below are based on Ian's reported tests plus private and public correspondence. The text is mostly Ian's, any long commentary by Herb is in []'s. Most of the text is from the May 2017 tests; I've folded in the July 2017 tests. - Herb

Complete Test Results

The May 2017 test results are in this linked text file. In addition, there's commentary and correspondence about the tests, from either private correspondence or from posts in cosmacelf Yahoo.

The July 2017 test results are in this linked text file.

Circuits and Test Conditions

Processors: 18 chips were tested. 9 genuine RCA CDP1802AE, 6 genuine RCA CDP1802ACE and 3 Chinese sourced and likely RCA CDP1802ACE re-marked as Intersil CDP1802ACE chips. Ambient temperature during testing was 18-20 degrees C.


"breadboard" test rig, Vcc = Vdd, 3MHz clock.

The EElf schematic is at Spare Time Gizmos Web site, the Embedded Elf.

On a solderless breadboard: a 74C240 tristate buffer, with outputs connected to the data bus enabled by !MRD. An 8 way DIP switch and 8 pullup resistors were connected to the 74C240 inputs. The 20H instruction (DEC R0) and forced tight loop (R0 is program counter) was created accordingly.

The 3 MHz CPU clock was provided by the VCO part of a 74HC4046 running at 5V. The output was upshifted to the applied Vcc voltage, by a DS75361 bipolar level shifting IC, into the clock pin 1 of the 1802. I used the second half of the 75361 driver, to up-shift the !RESET output of a MAX1232 to Vcc, for the !CLEAR on the 1802 for a power on reset. [From private emails from Ian to Herb.]

See Technical Comments near the end of this document for more details.


"EElf" test rig, Vdd > Vcc, Vcc=5.0V

Modified wire wrapped version of a Spare Time Gizmos' Embedded Elf (EElf). It is running at various crystal-selected frequencies, [with a seperate Vdd power supply]. 32K each of RAM and ROM, 10K data bus pullup resistors, and the EF3/Q bit basher used for serial communications. Two 0.5 Ohm 1% resistors inserted into the Vcc and Vdd paths to measure current, with bypass caps either end. [Icc was measured differently in May versus July, see notes with the data.]

The 1802 clock is driven by the standard 1802 crystal circuit across pins 1 and 39, exactly the same as the published EElf circuit - 10M resistor, two 22pF capacitors and a crystal. The EElf has a MAX705 driving !CLEAR rather than a DS1233, because I had one and I wanted the reset switch to be de-bounced. [From private emails from Ian.]

A boost DC-DC converter module with potentiometer provided variable Vdd. A 1N5819 Schottky diode was connected forward-biased, between Vdd (cathode) and Vcc (anode) to avoid Vdd less than Vcc. Programs run were "waiting for CR" and "memory test".

See Technical Comments near the end of this document for more details.

Test results

breadboard, Vcc=Vdd, 3Mhz, run 20H instruction
May 2017 results (table 2)

Vcc=Vdd	Icc		Idd
5.0	.35-.39		.76-.94
6.5	.49-.55		1.12-1.41
10V	.81-.91		2.09-2.74
12V 	1.03-1.12	2.73-3.61
15V	1.36-1.49	3.78-5.10

EElf test bed, RAM/ROM Vdd > Vcc results
Vcc=5V, waiting for CR, 3.072 MHz
10K pullups on data lines, Icc includes pullup current.
May 2017 results.(Table 3)

Vdd	Icc	Idd
5V	2.2-2.6	1.10-1.40
10V	2.2-2.4	2.78-3.70
12V	2.2-2.4	3.66-4.86
15V	2.2-2.6	4.98-6.76

Analysis: Icc has increased ~6 times likely due to driving the 10K data bus pullup resistors and /EF3 10K pullup resistor, all to 5V. [i = 5V/10Kohm = 0.5mA when a line was "low" at any moment.]

Table 3A: results from July 2017, measurements of processor current only. 10 micro Volt resolution meter used to measure both Icc and Idd. Otherwise similar test conditions:

Vdd  Icc range  Idd range
5V   0.54-0.76  1.10-1.34
10V  0.52-0.78  2.76-3.66
12V  0.48-0.78  3.60-4.80
15V  0.44-0.74  4.94-6.68

[Note from Herb: Icc difference from May to July, roughly about 1.6-1.8mA, was likely due to 5V pullup resistors as noted.]

Table 4: EElf test bed for max reliable speed
- Icc1, Idd1 Waiting for CR (part 1), Icc2, Idd2 RAM test (part 2)

May 2017 results: Icc includes pullup current and .5ma from 10K pullup on /EF3 serial-in line Vcc=5V. Current in mA. Frequency range in MHz. On chip oscillator used.

Vdd  Icc1 range Icc2 range  Idd1 range   Idd2 range  Freq range
5V   3.6-4.0    3.8-4.4     2.56-3.70    3.72-5.26   6.74 to 8.86MHz
6.5V 3.8-4.4    4.2-5.0     4.90-7.12    6.78-9.80   8.86-12.28MHz
10.0 4.2-4.8    4.8-5.4     13.04-17.04  17.14-22.12 13.1-16MHz
12v  4.4-5.0    5.0-5.8     18.28-25.42  23.54-32.66 14.31-18.43MHz

July 2017 results, maximum crystal frequency for on-chip oscillator. Icc does NOT include 5V pullup current from data or contol lines. /EF3 is NOT connected to serial port, so no pullup current. Same frequency crystals used as in May 2017 measurements, to allow direct comparison.

Vdd  Icc1 range Icc2 range  Idd1 range   Idd2 range  Freq range
5V   1.00-1.60  1.42-1.90    2.50-3.68    3.68-5.26   6.74-8.86
6.5V 1.22-1.74  1.66-2.32    4.88-7.12    6.76-9.84   8.86-12.28
10V  1.64-2.14  2.20-2.76   13.00-17.04  17.08-22.16  13.10-16.00
12V  1.76-2.30  2.36-3.06   18.26-25.42  23.66-32.88  14.31-18.43

Maximum frequency range with expanded set of crystals at Vdd=12V, more than 128 successful passes of RAM test, was 14.46-19.20 MHz

[comment by Herb: Icc difference from May to July suggests a current of about 2.6-2.7ma due to data-line pullups and /EF3 pullup, all 10K ohms, to 5V, .]

In later tests of the EElf circuit, cooled and uncooled, Ian achieved higher sustained clock speeds..

Ian's technical comments, summary

There were 2 failure mechanisms with the DEC 0 system due to excessive clock speed. One was the TPA generating system dropping clocks i.e. sometimes there would be 9 clock cycles between TPA pulses. The other was MA0 going high during the A8 data period. I.e. instead of the address going from 0000 to 0001 it would suddenly change to 0100 or to 0101. - Ian, May 2017. For further details, see the commentary following the May 2017 tests results..

In the May 2017 test results and commentary, Ian discusses markings on the 1802's versus his test results. He considers that RCA or Harris may have made a number of 1802 versions which aren't identified in RCA or Harris documentation, but have different speed and current properties, due possibly to production changes like smaller die, etc.

Also in the May 2017 commentary, he discusses the likely consequences of running Vcc above 5 volts. Namely, you need voltage translation hardware, but it must run at speed. He also discusses the various clocking schemes, as noted in the summary above.

Ian said in May 2017, "I think mentioning the temperature is worthwhile. There will be a speed drop with temperature...I don't want to mislead people trying to achieve similar results in a room 30 Celcius." See the notes on Ian's videos for more temperature information.

In Private correspondence from Ian, 1 Jun 2017: "You mention [in correspondence] "B" devices. I have 5 from a Chinese eBay seller. They have all been relabelled with the underside markings scratched out, two were DOA, two fit into the "Gen II" <= 20 MHz @ 12V class and one is one of the "Gen III" very fast class. There was nothing obvious in the measurements to distinguish them from any other chips and because of the relabelling who knows what they were originally."

"[And] as far as ceramic package ones are concerned, I have a total of 12 and the last few that I bought as used from a Chinese eBay seller are in the high performance category. That source is still available which is more useful to other people than the one-off "all they had" purchases I made for the others. - Ian

Ian in private correspondence during June, noted that Icc in the EELF-like setup, included current from the 10K pullup resistors, for both the data lines and the control lines. They only drew current when those lines were pulled low. Ian and I discussed the control lines; only the /EF3 serial-in line would have been low, during serial-idle conditions, which were continuous. That accounts for 5V/10K = .5mA constant current, we concluded.

As for the eight data lines, a first-order estimate is that half the lines are low, half the time - 8 / 2 / 2 * .5mA, or 1mA. Allison Parent, pointed out in a post, the data line drivers draw more current, while in the linear-operating region between high and low. That depends on switching time and clock frequency. Consequently, Ian ran the experiment again in June 2017, to measure actual current less the pullup current.

And in the July 2017 results above, they show a rough constant difference of 2.6 to 2.7mA - Herb

Related commentary on TPA

In followup discussion by Ian May in cosmacelf Yahoo, he asks in a July 2017 thread "Overclocking: what would YOU like measured? " about additional testing at speed and voltage. In his discussion and responses, he notes the value of using a delay line for TPA. At some point, I may add a link here to summary notes from that discussion. In addition, from prior work by Ian, he suggests the value of adding a 74LS367 to clean up the TPA signal. He posted in the cosmacelf file area under "Ian May", a PDF of oscillographs of buffered TPA for input and output. The 74LS367 essentially 'squares up' the signal, and so makes the TPA look "earlier". - Herb

Also look at notes associated with Ian's videos of the EElf, for discussion of TPA and clock. - Herb

Low temperature and high speed: Ian's video


Ian made videos of high-speed operation of his EElf circuit, with a uncooled and cooled CPU. There's additional details in those videos about his operation of his EElf circuits. Ian provided me with an emailed summary of the videos Later he posted a summary in cosmacelf, and with the videos; which I've edited into this document. Here's a photo of Ian's EElf circuit. They were posted to YouTube, June 27 2017, and updated later.

first video is here 9:27 ~ 190 MB. The title is "Overclocking & overvolting a CDP1802ACD microprocessor". The second video is here 7:51 ~ 180 MB. The title is "Overclocking & overvolting a cooled CDP1802ACD microprocessor". Quoting Ian: "[The first video is] showing my STG EElf, running with my best CDP1802ACD, at maximum reliable clock speeds. In the second video I have [the same setup plus I've] attached a Peltier heat pump module to the metal plate on the top of the 1802 package, to reduce the temperature of the chip to below ambient."

The non-cooled Harris 1802 runs at 3MHz and 30Mhz with Vdd at 12V; running temperature is 31.6 Celsius or 88.88 degrees Fahrenheit; Vcc current is ~5mA and Vdd ~45 mA. The cooled Harris 1802 fails at 36MHz but succeeds at 35Mhz with Vdd at 13V; cooled temp is -14 C or 6.8 F; the peak Vdd current is 58mA. TPA timing signal for both, is delayed 12nS by a Maxim DS1100Z-20 delay line, SO-8 package. The cooler, is a one-stage Peltier device and a socket 7 heatsink from an old PC.

Cooler: "Clockwise from top left: Pentium 1-class [Socket 7] heatsink and fan. CPU socket with clip mounting points attached with hot-melt glue. Another clip (from a Pentium 4 478-pin heatsink) showing the central tensioning spring. Polystyrene insulator for the sides of the CPU. Aluminium heat spreader and shim placed between the TES1-7103 Peltier module [blue & red leads] and the metal plate on top of the CPU package. Polystyrene insulator surround for Peltier module and heat spreader. In the centre, polystyrene insulator strip for CPU underside." - Ian May

Ian describes the cooler as a "sub-optimal solution"; he suggests the CPU socket might be constructed from a pair of single-row pins, with an improved insulator under the package.

In Aug 10 2017, Ian posted these general comments about running standard 1802's at higher speeds and higher Vdd.

"No it's actually getting quite a thrashing, because it is a CDP1802ACD which is a 5V part. The test results from the [prior] comparison between Vdd=10V and Vdd=5V RCA 1802As', showed that there was no obvious differences between them. So I've been (carefully) testing other 5V ones at Vdd=12V or more. I have found a few that have a problem with the Elf2k BASIC above a certain voltage, the lowest so far is 10.9V, but I haven't destroyed one yet. Thirteen Volts was really pushing things, as without cooling going above 12V, usually results in higher temperatures rather than higher clock speeds.

"I think I can probably do better with a system designed to use a cooler right from the start rather than a "retro-fit" version. [Mentions better insultation.] How long these chips can take this level of abuse is a good question. ....It will likely be a case of waiting for one to fail. If one does fail, and if it is in a ceramic package, it should be possible to remove the metal top plate and give the die and wire bonds an inspection." - Cheers, Ian.

Further information about the video may be available with it, or in posts or documents at the cosmacelf Yahoo discussion group Web site. View the video at full size, to catch the details. - Herb Johnson

Tests by Denny Rugenstein, Oct 2019

[Herb's edits are in []'s. The follow is Danny's posted results from the source cited above.]

My interest was in evaluation of Lee's Membership Card set so I used the same [DC power] voltage for all ten ICs. The Membership card set used is: CPU card Ver. K2 and Front card Ver. J. The circuitry is both cards are soldered to a homemade backplane with some space between the cards (for access to the chips on the CPU card). Additionally, a crystal oscillator using a CD74HCT00 gate is on the side of the cards at the backplane, to provide a clock from 1 MHz to 20+ MHz. The resonator is removed and the external clock is routed to the bottom resonator hole. [Lee's kit consists of HCT logic IC's. RAM was not specified.] The CMOS crystal oscillator was placed on the backplane near the CPU card because the resonator was flaky when measuring the frequencies with my multimeter. Keep in mind that this work was done at room (72 F) temperature.

Speed tests

From my stock of crystals, 2 MHz to 20.0 MHz were evaluated. The minimum voltage which would support Lee's Q slow blink program was determined for each crystal.

MHz          1802 Voltage        1806 Voltage
2.00           3.49                     3.49
4.00           3.49                     3.49
6.176          3.52                     3.49
8.00           4.00                     3.49
10.00          4.53                     3.49
12.00          5.20                     3.98
13.30          5.64                     4.35
14.40          6.20                     4.63
14.73          6.35                     4.76
16.00          null                     5.15
18.00          null                     6.75
20.20          no run                   no run

After replacing the destroyed [1N5231 5.1V zener] protection diode [across the Vcc] with a 1N5236 [7.5V zener] diode, the membership card set works well.

One further note, I allowed my Membership Card set to run unattended for 24 hours. The voltage (Vcc=Vdd) set at 6.66 volts and 18MHz crystal executing Lee's slow Q blink program revealed that the CDP1806ACE (RCA Z 810) ran without fail and developed not noticeable temperature increase.

The conclusion [from this test] is that the "slow" 1802 is not slow at all and the 1806 is faster at lower voltages. Since the limit for CMOS chips is 7.0 volts, no experimentation was done at higher voltage. Your results may vary.

Minimum Voltage at 10MHz

For this CPU chip to chip variation study, the clock was 10.000MHz throughout. The minimum voltage to execute Lee's slow Q blink program was determined by noting the lowest voltage which would sustain a blinking Q LED. In summary, Vcc = Vdd = (3.0 volts to 6.75 volts). Following below is the voltage, then the marked Brand and Date Code.

CDP1806ACE                   CDP1805ACE               CDP1802ACE
3.73v  RCA 914               3.48v  RCA 910            3.98v  Harris J9414
3.97v  Harris 9242           3.62v  RCA 910            4.35v  Harris J9132
3.62v  Harris 9516           3.82v  RCA 910            3.71v  Harris J9128
3.91v  Harris 9441           3.45v  RCA 910            3.91v  Harris J9506
3.66v  Harris J105           3.75v  RCA 910            3.66v  Harris J9429
3.66v  Harris H9518          3.64v  RCA 910            4.39v  Harris H9517
4.02v  Harris J9438          3.57v  RCA 910            4.37v  Intersil H0745
3.51v  Intersil H0820        3.77v  RCA 910            4.74v  Intersil H0745
3.50v  Harris J9214          3.62v  RCA 910            3.86v  Intersil H0745
3.84v  Harris J311           3.60v  RCA 910          
3.63v  Harris H9536          3.72v  RCA 927
3.49v  RCA 810

RCA avg = 3.61v               RCA avg = 3.64v            Harris avg = 4.09v
Harris avg = 3.76v             11 chips                  Intersil avg = 4.32v
Intersil  = 3.51v                                           [9 chips]
12 chips 

Posted remarks by others

Posted remarks by others at cosmacelf / included the following. "How hot did the 1802 get?" as power consumption increases with voltage and with frequency. CMOS was a low-power low-clock design choice, so it's a reasonable question. It was noted that the early RCA 2MHz specification was at a time when CMOS ran slowly at 5 volts, and RAMS and ROMs ran at a few or several MHz. It was also noted (by Ian May) that running the RAM above 5V may have been above its specifications.

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