Date: Sun, 16 Jul 2017 From: ian may To: Herb Johnson Subject: Re: Challenge: 1802AE vs 1802 ACE Hi Herb - it has taken longer than I expected to produce the new results but I have just sent a new message to the group. I have changed the wiring and redone the measurements and this time I used the 10 micro Volt resolution meter to measure both Icc and Idd. I've also added a new table showing maximum clock frequency with my new set of crystals versus the previous measurements. At the top of the attached text file is a data summary showing the data you were intending to put on your web page (if I remember correctly). If there is some other data reduction or anything else you need please let me know.Cheers, Ian. Date: 24 Jul 2017 From: Ian May To: Herb Johnson My own typo in the July measurements - the Idd2 entry for device 18 at 10 V is 22.14 which should be 22.16 to agree with the earlier summary. I had worked out the upper and lower limits and wrote them in my notebook (a paper one that is) and then made the typing error when entering the table the table. =================================== Summary of EElf test bed results Test condition 3.072 MHz crystal on-chip oscillator Vcc=5V Current in mA "waiting for CR" Vdd Icc range Idd range 5V 0.54-0.76 1.10-1.34 10V 0.52-0.78 2.76-3.66 12V 0.48-0.78 3.60-4.80 15V 0.44-0.74 4.94-6.68 Test condition maximum crystal frequency on-chip oscillator Vcc=5V. Current in mA. Frequency range in MHz Vdd Icc1 range Icc2 range Idd1 range Idd2 range Freq range 5V 1.00-1.60 1.42-1.90 2.50-3.68 3.68-5.26 6.74-8.86 6.5V 1.22-1.74 1.66-2.32 4.88-7.12 6.76-9.84 8.86-12.28 10V 1.64-2.14 2.20-2.76 13.00-17.04 17.08-22.16 13.10-16.00 12V 1.76-2.30 2.36-3.06 18.26-25.42 23.66-32.88 14.31-18.43 Maximum frequency range with expanded set of crystals at Vdd=12V 14.46-19.20 MHz Raw data tables EElf test bed Icc and Idd in mA vs Vdd Frequency 3.072 MHz Vcc=5V "waiting for CR" Dev Vdd=5V Vdd=10V Vdd=12V Vdd=15V No Icc Idd Icc Idd Icc Idd Icc Idd 1 0.54 1.10 0.52 2.82 0.48 3.72 0.44 5.22 2 0.66 1.20 0.56 3.08 0.56 4.00 0.52 5.50 3 0.64 1.14 0.54 2.76 0.54 3.60 0.52 4.94 4 0.60 1.28 0.56 3.10 0.56 4.02 0.52 5.50 5 0.60 1.12 0.58 2.84 0.56 3.72 0.54 5.12 6 0.76 1.24 0.78 3.10 0.78 4.02 0.74 5.48 7 0.60 1.14 0.60 3.02 0.60 3.88 0.56 5.32 8 0.56 1.14 0.56 3.06 0.56 3.94 0.56 5.40 9 0.60 1.16 0.58 3.10 0.58 4.04 0.56 5.48 10 0.62 1.34 0.60 3.66 0.56 4.80 0.56 6.68 11 0.58 1.14 0.56 2.92 0.54 3.82 0.52 5.24 12 0.58 1.20 0.54 3.10 0.60 4.02 0.52 5.50 13 0.62 1.20 0.56 3.10 0.60 4.04 0.54 5.56 14 0.62 1.16 0.54 3.02 0.54 4.00 0.54 5.60 15 0.60 1.12 0.52 2.82 0.52 3.66 0.54 5.04 16 0.64 1.30 0.56 3.30 0.56 4.30 0.58 5.94 17 0.64 1.20 0.58 3.10 0.58 4.02 0.60 5.52 18 0.68 1.28 0.60 3.30 0.64 4.30 0.60 5.90 EElf test bed Frequency Icc and Idd in mA vs Vdd 5V and 6.5V Vcc=5V Icc1/Idd1 "waiting for CR" Icc2/Idd2 TEST RAM Dev Max -------Vdd=5V-------- Max ------Vdd=6.5V------- No Freq Icc1 Icc2 Idd1 Idd2 Freq Icc1 Icc2 Idd1 Idd2 1 7.15 1.00 1.44 2.56 3.68 10.00 1.30 1.86 5.04 6.92 2 6.74 1.04 1.42 2.64 3.92 8.86 1.34 1.66 5.22 6.88 3 7.15 1.06 1.46 2.50 3.70 10.00 1.34 1.82 4.90 6.76 4 7.68 1.20 1.60 3.06 4.36 10.00 1.38 1.86 5.50 7.46 5 7.37 1.10 1.50 2.72 3.96 10.00 1.34 1.86 5.04 7.04 6 7.37 1.30 1.76 2.90 4.20 10.00 1.54 2.10 5.66 7.56 7 8.00 1.30 1.68 3.02 4.32 11.34 1.50 2.06 5.96 8.22 8 7.68 1.16 1.62 3.00 4.28 10.00 1.32 1.86 5.34 7.34 9 8.00 1.26 1.68 3.08 4.44 11.00 1.52 2.02 5.94 8.22 10 6.74 1.14 1.64 3.00 4.36 8.86 1.30 1.76 5.50 7.58 11 7.68 1.16 1.60 2.88 4.18 10.00 1.34 1.88 5.24 7.22 12 6.74 1.06 1.46 2.68 3.92 8.86 1.22 1.76 4.88 6.92 13 8.00 1.30 1.70 3.14 4.54 10.00 1.40 1.90 5.46 7.44 14 7.37 1.12 1.56 2.80 4.10 10.00 1.36 1.84 5.32 7.60 15 7.37 1.06 1.50 2.66 3.86 10.00 1.34 1.84 4.96 6.90 16 8.00 1.30 1.74 3.32 4.74 11.34 1.56 2.20 6.54 9.00 17 8.00 1.32 1.76 3.16 4.56 11.34 1.56 2.18 6.30 8.52 18 8.86 1.60 1.90 3.68 5.26 12.28 1.74 2.32 7.12 9.84 EElf test bed Frequency Icc and Idd in mA vs Vdd 10V and 12V Vcc=5V Icc1/Idd1 "waiting for CR" Icc2/Idd2 TEST RAM Dev Max -------Vdd=10V------- Max -------Vdd=12V------- No Freq Icc1 Icc2 Idd1 Idd2 Freq Icc1 Icc2 Idd1 Idd2 1 14.31 1.72 2.36 13.08 17.08 15.36 1.80 2.38 18.26 23.66 2 13.10 1.64 2.20 13.00 17.28 14.74 1.84 2.50 18.94 24.46 3 14.74 1.88 2.46 13.18 17.24 16.00 1.90 2.56 18.56 24.20 4 14.74 1.88 2.52 14.60 19.04 16.00 1.96 2.60 20.64 26.46 5 14.74 1.86 2.50 13.68 17.82 16.00 2.00 2.64 19.00 24.70 6 14.31 1.96 2.70 14.00 18.16 16.00 2.12 2.90 20.14 25.96 7 16.00 2.10 2.70 15.32 19.96 18.00 2.16 2.94 22.30 28.92 8 15.36 1.90 2.56 14.88 20.72 16.00 1.94 2.60 20.04 25.98 9 15.36 1.96 2.54 15.16 19.66 16.00 2.00 2.62 20.38 26.44 10 13.10 1.82 2.32 14.90 19.48 14.31 1.86 2.46 21.12 26.84 11 15.36 1.86 2.54 14.50 19.12 16.00 1.90 2.66 19.50 25.56 12 13.10 1.68 2.26 13.10 17.34 14.31 1.76 2.36 18.50 23.90 13 15.36 1.92 2.56 15.12 19.62 16.00 2.00 2.66 20.30 26.40 14 14.31 1.80 2.40 13.74 18.04 15.36 1.86 2.48 19.16 24.80 15 14.74 1.78 2.50 13.36 17.70 16.00 1.96 2.58 18.74 24.46 16 15.36 2.00 2.60 16.30 21.34 16.00 2.06 2.74 22.16 30.36 17 16.00 2.06 2.72 15.92 20.88 18.00 2.24 2.96 23.16 30.10 18 16.00 2.14 2.76 17.04 22.16 18.43 2.30 3.06 25.42 32.88 EElf test bed maximum frequency in MHz at Vdd=12V with expanded set of crystals more than 128 successful passes of RAM test Dev Prev New Next No max F max F crystal 1 15.36 15.74 16.00 2 14.74 15.00 15.36 3 16.00 16.93 17.73 4 16.00 16.38 16.77 5 16.00 16.77 16.93 6 16.00 16.25 16.38 7* 18.00 17.73 18.00 8 16.00 16.77 16.93 9 16.00 16.93 17.73 10 14.31 14.46 14.74 11 16.00 16.25 16.38 12 14.31 14.46 14.74 13 16.00 16.77 16.93 14 15.36 15.74 16.00 15 16.00 16.38 16.77 16 16.00 16.93 17.73 17 18.00 18.00 18.35 18 18.00 19.20 19.66 * Device 7 was down-rated.