Ian May, description of videos of two (uncooled and cooled) modified EELF COSMAC circuits for high-speed operation of a Harris 1802 CPU. This document last updated July 31 2017, edited by Herb Johnson The information below is from a private email by Ian May on July 28th, and as posted by Ian in cosmacelf Yahoo on July 29th 2017 under "I have uploaded 2 videos of my EElf to YouTube". I've edited these descriptions for brevity and clarity. There's also a brief text description with the first video. Further disucssion of Ian May's work is on this Web page of my Web site: http://www.retrotechnology.com/memship/1802ACT_tests.html - edited by Herb Johnson, my edits are in []'s. ------------------- I have uploaded to YouTube, two videos I made showing my STG EElf running with my best CDP1802ACD at maximum reliable clock speeds. In the second video I have attached a Peltier heat pump module to the metal plate on the top of the package to reduce the temperature of the chip to below ambient. I recommend selecting "Theatre mode" for best text readability. The first video is here https://youtu.be/tWqG44yyJ0k 9:27 ~ 190 MB The title is "High frequency operation of an 1802 processor.". The second video is here https://youtu.be/xtvpMTW6c3E 7:51 ~ 180 MB The title is "High frequency operation of an 1802 processor with cooling.". I have attached to the video posts, two still shots of the board taken after each video recording was finished but with the board still running. Since the Peltier, heatsink and fan assembly made the board front heavy I had to leave the board horizontal which results in the POST LEDs being mostly obscured. The movies were recorded by a digital still camera with a movie mode. They have been recorded in 1280x720p @ 30 frames per second. I am neither a movie producer or a video camera operator so don't expect much. The LED time clock is there to show the total elapsed time... [Details of the video format, and some features of Ian's instruments, are mentioned in Ian's cosmacelf post. Also see the comments below.] VIEWING: Since you will be trying to read text on a 19" monitor in 640x480 mode that occupies roughly half the frame I would recommend viewing at 1280x720. "Theatre mode" gives the best text readability on my screen. TPA AND CLOCK: The TPA signals shown on the oscilloscope originate from the 20 nS output of the DS1100-20 delay line. The TPA signal to the high address latch comes from the 12 nS output of the DS1100-20. The clock signal on the oscilloscope is the output from one of the 74HC00 gates [of a 74HC00 based crystal oscillator] and not the reduced amplitude clock signal being fed into pin 1 of the 1802. The loading of the oscilloscope and frequency counter probes affected the signal to pin 1 if they were connected to it and caused the 1802 to fail. This particular CDP1802ACD chip has no problem running with the higher frequency crystal shown in the first video in the on chip crystal oscillator, but pin 39 is unable to drive a single input of the 74HC00 (bottom left of the board). I decided it was better to show the clock frequency on the frequency counter rather than TPA so I used the 74HC00 based crystal oscillator. CURRENT AND POWER: In the first video, at the [30Mhz] higher frequency, the Vdd current is ~44mA, with Vdd at 12.1 Volts. So the Vdd component of the power dissipation is ~530 mW. I have since taken some measurements of the package temperature using the thermocouple and found that the highest temperature point is 31.6 degrees C, which is a 15.3 degree rise above the 16.3 C ambient temperature (as measured by the thermocouple). In the second video the Vdd current is ~58mA at the final frequency with a Vdd of 13 Volts so the Vdd component of the power dissipation is ~750 mW. TEMPERATURE: In the second video ..the LCD display instrument between the frequency counter and the oscilloscope.. is a thermocouple thermometer. The thermocouple is resting on the edge of the metal plate on top of the 1802. [Ian describes it's hard to read this display.] At the point where I turn on the EElf, the temperature display is showing -16.7 degrees C. When the first errors are printed the temperature has risen to -14.0 C. When I change to the lower frequency oscillator the temperature has dropped to back to -15.0 C at switch on. The temperature stabilizes at -13.9/-13.8 C over the two hour run time. DISCUSSION OF RESULTS: For people who are having trouble believing what they are seeing I offer the following information. When I posted a message to the group about the time per pass for the memory test in a v88 Elf2k ROM, Dave Ruske reported that his system [with a clock frequency of 3.579 MHz divided by 2 (1.789 MHz)] took approximately 55 seconds per pass; which works out to 55*1.789 or 98.4 seconds per MHz. Mark Abene confirmed my calculation that at 8 MHz his 1806 system took 12.6 seconds per pass so that gives 12.6*8.00 or 100.8 seconds per MHz. If you download the videos you can use your favourite video editor to measure the time per pass by counting individual frames if needed. You can also use the LED time clock to measure the elapsed time for a given number of memory test passes. Both videos consist of a continuous recording followed by two short sections recorded at near one hour and more than 2 hour intervals. I assumed you would not like to watch a memory test for over 2 hours. The LED time clock is there to show the total elapsed time so if you make a note of the time at the start of the final memory test [TE RAM] command and subtract it from the time at the end of each video you can work out the time per pass by dividing the elapsed time by the number of passes. Divide the above 98.4 or 100.8 seconds per MHz by the calculated time per pass and you should have the approximate 1802 clock frequency in MHz. The other check that can be applied is that every time I turn the system on I issue a SHOW TERM [SH TERM] command which lists the constant being used by the EF3/Q bit banging routines. Minicom clearly shows the serial transmission rate in use so people familiar with the Elf2k bit banging routines [Mike Riley and Bob Armstrong at least] should be able to roughly calculate the 1802 clock frequency based on the serial transmission speed and the results of the SH TERM commands. The values for each video are as follows (assuming you are having difficulty reading them from the video) first video second video 1st SH TERM 0x0D 1st SH TERM 0x35 2nd SH TERM 0xBD 2nd SH TERM 0x33 3rd SH TERM 0x09 - Ian May, as told to Herb Johnson and as posted in cosmacelf ------------ July 30 2017, posting in cosmacelf in response to questions about possible 1806 operation. This edited content is about the 1802 tests only. - Herb For the 1802ACD in the videos under different conditions, here are some maximum frequencies [versus TPA delay]. Tests were done for more than 128 passes of TEST RAM program. abbreviations oco - on-chip oscillator fclk - CMOS levels full amplitude clock pclk - padded (reduced amplitude) clock ~ 3.6V TPA direct to '373 latch Vdd 5V 14.46MHz oco 14.46MHZ fclk 14.756MHz pclk TPA delay 4nS (~same as a chip buffering it) Vdd 5V 15.00MHz oco 15.00MHz fclk 15.00 MHz pclk TPA delay 20nS Vdd 5V 16.00MHz oco 15.36MHz fclk 16.00MHz pclk TPA delay 12nS Vdd 12V 30.00MHz oco 22.12MHz fclk 30.00MHz pclk The last line shows why you need to try all possible combinations under all conditions. It would have been easy to conclude that the full amplitude clock would do from the 5V measurements but you would have missed out on a serious performance boost for the 12V case if you didn't try the on-chip oscillator as well. If I was guessing what an 1806 might do with a delayed TPA slightly over 16.00Mhz looks possible. The Peltier cooler got the 1802 to almost 36MHz from 30MHz without it. That is ~ 20% so that suggests a maximum for an 1806 of 19.2MHz. If you were executing 1806 code then for the RLDI instruction which is 5 cycles, an 1802 would use 8 cycles, then to outrun the 1802 at 30MHz the 1806 would need to be doing 5*30/8 or 18.75 MHz. I'd think it would be up to the SCAL and SRET instructions to get the majority of any gain over a faster 1802. For something like a Forth, that doesn't need to use standard call and return subroutines, the 1802 would easily run over the 1806 running at a >50% higher clock speed, and if you were executing 1802 code anyway the same would apply. In summary - don't get you hopes up too high for an 1806, the speed boost that this particular 1802 gets from a 12V Vdd is nearly 100%. - ian