Correspondence from Ian May and others, about his 1802 voltage and current tests as posted May 27 2017 in cosmacelf Yahoo. Provided here by Herb Johnson, with permission from Ian May. Corrections July 24 by Ian May. This document last updated July 24 2017 by Herb. "Challenge: 1802AE vs 1802 ACE - which is which?" Posts in cosmacelf Yahoo, as dated and authored. fps16xn3 [Ian's posting ID] May 27 2:14 PM I've spent some time taking measurements of some 1802AE and 1802ACE chips. The challenge is - using the data that I have measured and provided below can you tell me which device is an 1802AE and which is an 1802ACE? The rest of this message is also included in the text attachment because of the high probability of the data table formatting being destroyed. Open the text file if that is the case. Any and all comments welcome. Cheers, Ian. [Testing report attached by Ian.] I had always assumed that CDP1802A chips were ones that had been tested at the maximum supply voltage (11V), whereas CDP1802AC chips were ones that failed testing at 11V but operated as per the data sheets at 7V maximum. The assumed result of this would be that there would be some 1802AC chips that could be operated successfully at voltages above 7V and below 11V. In an attempt to verify this assumption I have taken measurements on a number of CDP1802AE and CDP1802ACE devices. Remember that the data sheet clock frequency specifications apply over a -40 to +85 degree Celsius temperature range. I'd find 85 degrees a tad too warm, so my data was measured at a room temperature of between 18 and 20 degrees Celsius. A total of 18 chips were tested, 9 genuine RCA CDP1802AE, 6 genuine RCA CDP1802ACE and 3 Chinese sourced re-marked (RM) chips that still retain the underside markings that are similar to those of the genuine RCA chips. The RM chips have had the Intersil logo applied and labelled as CDP1802ACE with "H0915" below in an attempt to pass them off as made in the 15th week of 2009. The 3 RM chips were added to make up an equal number of 9 of each type but there is always the chance that they were in fact originally CDP1802AE chips rather than CDP1802ACE. The underside markings are listed in table 1 below. These may allow you to identify devices that you have which may achieve test results similar to those that I have. BTW - The first 9 devices were the RCA CDP1802AEs, devices 10-15 were the RCA CDP1802ACEs and devices 16-18 were the RM CDP1802ACEs. Two different test rigs were used to obtain the results shown below. For the tests where Vcc and Vdd were equal, a solderless breadboard was used with a 74C240 tristate buffer connected to the data bus and enabled by !MRD. An 8 way DIP switch and 8 pullup resistors were connected to the 74C240 inputs. My original intention was to select the NOP instruction via the DIP switches. Nothing was connected to the address bus. Every processor fetch would read the same data i.e. NOP and the address bus would simply cycle from all zeros to all ones. After some thought I realised that the 1802's unique architecture would allow a couple of different options. By setting the DIP switches to DEC R0 (20H) the first fetch cycle after reset would increment R0 and execution of the DEC R0 would decrement R0 back to zero. Similarly STXD (73H) would cause the address bus to cycle in the same way while a write cycle would be performed during the execute phase. The usual 10K Ohm data bus pullup resistors were not used so with this setup the chip is only driving stray capacitances and as a consequence the Vcc currents are much lower than for the second test rig. The CPU clock (frequency 3 MHz) was provided by the VCO part of a 74HC4046 upshifted to the applied Vcc voltage by a DS75361 bipolar level shifting IC. The second test rig was a modified wire wrapped version of a Spare Time Gizmos' Embedded Elf (EElf). http://www.sparetimegizmos.com/Hardware/ Elf2K_Accessories.htm#The%20Embedded%20Elf [data bus: 10K pullups, 74HC373, 27C256, 62256. address bus 2nd 74HC373, same 27C256, same 62256. Ian adds "Actual devices used for testing Toshiba TC55257CPL-10 100 nS 32kBx8 RAM, Winbond W27E257-12 120 nS 32kBx8 EEPROM."] The minimum hardware configuration was used with 32K each of RAM and ROM and the EF3/Q bit basher used for serial communications. Two 0.5 Ohm 1% resistors inserted into the Vcc and Vdd paths allow the currents to be measured (these have filter capacitors to ground at the Vcc and Vdd pins). A boost DC-DC converter module (from eBay marked MT3608 on the underside of the PCB) with a multiturn potentiometer allowed the desired Vdd to be selected. Vcc was always 5V. NOTE: Whilst I have largely ignored some of the data sheet voltage specifications during this testing I took particular care to make sure that the Vdd70% of Vcc and a logic zero is <30% Vcc as per standard CMOS. I didn't try it on the breadboard, but I expect that the using the on-chip oscillator would be fine no matter what Vcc is (I should probably verify this at some stage). Because I was using the 74HC4046 to drive the clock (so I had a continuously variable clock) I had to shift a logic 1 from a nominal 5 volts to at least >70% Vcc before I could feed it into pin 1 on the 1802. [Ian previously reported, he used a DS75361 to drive the 1802 clock, from the 74HC4046. - Herb] I have obtained a few different types of CMOS low to high voltage translators. But, according to the data sheets they are very slow and some require that the two supply voltages come up in a specific order (same as the 1802 higher voltage supply must always be higher than or equal to the lower voltage supply). The DS75361 is way faster and its Vcc2 is >4.75V and <24V. I had originally bought them because I was intending to see what was possible at Vcc=Vdd >5 Volts in a "full blown" 1802 system (assuming that this was the way to reach maximum clock frequency). The hardest thing to up-shift is the data bus, because you have to be able to tri-state the up-shifter. My planned solution was DS75361s followed by a 74C240 to do the "tri-stating". The delay through the 74C240 is around 60 nS. That looked usable, until I found those gen 3 1802s that run at 24 MHz and at that speed 60 nS is 1.5 clock cycles. So I don't think running Vcc=Vdd >5 Volts will yield higher speed, than can be obtained with sticking to the simple Vcc=5 Volts condition (and let the 1802 internals up-shift from 5 Volts to Vdd>5V). On the breadboard circuit, I used the second half of the 75361 driver to up-shift the !RESET output of a MAX1232 to Vcc for the !CLEAR on the 1802 for a power on reset. On the EElf, for the measurements I provided, I was using the on-chip oscillator as per the published circuit. Using jumpers I can also select a 74HC4046 VCO oscillator, an HC based gate oscillator that will (most times) run a third overtone crystal correctly and a socket for a 8 or 14 pin oscillator module. So in summary, for the breadboard "naked" 1802 a DS75361 translates the 5 Volt level output of the 74HC4046 VCO to the Vcc supply voltage of the 1802 feeding into pin 1 and for the EElf (where Vcc is always 5 Volts) the standard 1802 crystal circuit exactly the same as the published EElf circuit - 10M resistor 2 22pF capacitors and a crystal. - Ian Ian added June 11 2017, private to Herb: The MAX1232 and the DS75361 driving !CLEAR are on the breadboard with the 74C240 for the Vcc=Vdd=whatever. The EElf has a MAX705 driving !CLEAR rather than a DS1233 because I had one and I wanted the reset switch to be de-bounced (and I had misplaced the rest of the MAX1232s I have and found the MAX705s first).