Stacking two Rev D or later "Membership Card" CPU boards

Last updated May 7 2022. Edited by Herb Johnson, (c) Herb Johnson, except for content written by Lee Hart and others. Contact Herb at, an email address is on that page..

This Web page discusses changes to the Rev D or later Membership Card CPU boards, to stack them through the 1802 socket, to double ROM and RAM, and/or double I/O. Notes for stacking or modifying Rev C CPU cards are on another Web page. A previous version of this note may be useful for still earlier CPU boards. Refer to the Membership Card home page for the current revision of the kit and more information. - Herb Johnson

Stacking CPU boards

The dual CPU board option is for more I/O, and possibly more RAM/ROM options. This is done by sharing the CPU chip with a second CPU board connected to the first CPU's 1802 pins. That will share resources by re-addressing the I/O support chips and RAM and ROM on the second card. The second card's 30-pin connector, becomes a second I/O connector: do not connect the two 30-pin connectors! Beyond a second pair of I/O ports, one might double-up on wide or narrow RAM and ROM chips. Not described, one might use two ROMS and one RAM if addressing can be rewired. - Herb Johnson, May 2022.

Jan 2019, Lee Hart: The present [CPU board] design is set up to be used as a daughterboard. There are jumpers to change the I/O port. The memory jumpers can be set to accomodate chips on both boards (either smaller than 32k each, or use an I/O bit to bank switch them). On rev.K, you just leave out the resonator on one board. On the others, you cut the clock pin of the wire-wrap socket. The DMA-IN pin is also cut off the wire-wrap socket.

1. Stack two CPU boards through the CPU's 40-pin socket. This is accomplished by installing a 40-pin wirewrap socket for the CPU socket on the top board, and connecting it to the bottom board's CPU socket. This also supplies power to the second board.

a. Solder the wirewrap socket on the top board, with leads at least ???? inches long. Also cut off conflicting wirewrap pins as follows:

Pin 1 (CLOCK) of the wirewrap socket - so the clock on the lower board doesn't conflict with the clock on the upper board. See notes below about rev C.

b) Plug the bottom ends of the wirewrap socket into a socket on the lower MC card (which has no 1802, of course).

You can use the Molex sockets I supply for the 30-pin connector, though they would have the effect of offsetting the upper board by about 0.1". The wirewrap pins can be bent .1" to compensate. Or, use non-offset Molex sockets.

In Jan 2019, Lee repeated:The physical stacking is [still] a bit of a kludge. The one I built uses a standard wire-wrap socket for the 1802 on the top board. The lower board has female SIP socket strips that mate with the wire-wrap pins. I included the [DC power and ground] pins in the 30-pin headers and sockets to provide some additional stability. The second set of I/O port pins are not connected between the two boards. - Lee Hart

Herb suggests an alternative: Solder a machine-pin socket on the end of the wirewrap socket. Make sure it's "square" to the plane of the CPU board. Use a machine-pin socket on the lower board, and "stack" the two 40-pin sockets. You may/should want to include standoffs to hold the assembly together.

2. Jumpers to pick an I/O port address.
- With no cuts/patches, it has the same OUT4/INP4 addresses as the previous board.
- By cutting a trace and adding a patch wire, you can get three non-conflicting addresses.
- This allows two (or 3) Membership CPU Cards to stack with different I/O port addresses. - They MUST have different I/O addresses or there will be conflicts.

[I/O jumpers]

For Rev D and later CPU boards, there's convenient jumpers to change the I/O address. On the schematic, they are shown as "I/O port select" from CPU pins 17, 18 19 (N2, N1, N0) to pins 1 and 2 of U4A (4093). They are physically located on the back (non-component side) of the CPU board, under the pin 20/21 end of the 1802 CPU. The board as provided, jumpers the I/O select line only to "N2". To change the address, cut the trace between "I/O" and "N2", and jumper to "N0" or "N1". If you want to select two I/O lines, also cut the traces between the three common "I/O" pins; then connect the two pins on either "end" of the three to NO, N1, or N2. In these ways, you can select any I/O port except 0 and 7.

3. Address memory IC at 0-32k or 32-64k, on each card.. This option changed on Rev G and later which supports both a ROM and RAM of different size on one CPU board. There's a HI and a LO address pin, and a U2 and a U6 address pin. So either wide or narrow ROM/RAM sockets, can be addressed in high or low memory. Refer to your CPU board's manual for details. For more complicated schemes, such as two ROMS and one RAM chip in a "RAM window" of memory, you'll have to add some address-select circuity, not discussed in this note.

For Rev F, E and D, here's some considerations. Look at the schematic and manual for your revision CPU board, to get this right. There's also a Tech NOte about stacking byte-wide RAM and ROM chips which is informative.

"[For Rev F, E, D] I added a pad so transistor Q1 can be installed 2 ways:
- The default is just like the Rev C board. Memory is from 0-32k, and only active during TPB. - The second way puts memory from 32-64k. But it is active during the entire bus cycle, so power consumption will be higher (like the Rev.A board).See this tech note about the changes from Rev A to B, for an explanation.

There are 3 pads where the leads of Q1 go (gate, source, drain). I would add a 4th pad. Let me number these 4 pads 1-2-3-4.

1 = /CE of memory (drain of Q1, and pullup resistor)
2 = TPA (from 1802)
3 = A15 (from address latch)
4 = VSS (ground)

0000: Q1 goes in 1-2-3. gate = TPA, source = A15.
/CE goes low when A15=0 and TPA=1.
8000: Q1 goes in 1-3-4. gate = A15, source = ground.
Q1 inverts A15, which directly chip selects memory.

What Lee Hart said about stacking two Rev C boards

These notes may apply differently for CPU boards after Rev C, but suggest things to watch out for. - Herb, 2022

On the driven board:

Bring out N0, N1: Disconnect /MWR from header pin 11; and /WE from header pin 10. Short /MWR to /WE. The ROM is on this board so write control is unnecessary. Connect header pin 10 to CPU pin 19 to access N0; connect header pin 11 to CPU pin 18 to access N1.

ROM address in upper memory: location depends on size of RAM and ROM. Details may be tricky. But as 1802 uses page 0 space for reset, interrupt, and special addressing, RAM should be in low memory.

I/O adr 5: Break U4A connection between pins 1 and 2. Connect pin not connected to CPU pin 17 (N2), to CPU pin 19 (N0). Now U4A decodes I/O address 5 on this board. While this could be done on either CPU board, the front panel is programmatically accessable by N4 instructions; the front panel would be or is connected to the CPU board on top. So re-addressing I/O makes more sense on the "driven" CPU board on the bottom.

disable RUN: Disconnect U4D pin 11 from CPU socket pin 1 (CLK). Remove R2 and R1 potentiometer, and C1 either shorted or removed. U4D NAND gate is available for other uses. RUN line from header pin 13 available as external input. R6 must be removed or disconnected from /CLEAR line, possibly used as pullup to +5. R7 possibly changed from 1M as pull-down, C3 removed or not, D10 retained or shorted.

possible negative voltage pump from U4D: steal CLK from pin 1, to drive gate U4D, to create negative charge pump for negative voltage source for serial interface. Component space formerly used for RUN (C3, R7, R6, D10) may be useful.

disable DMA F/F: Diconnect CPU socket pin 38 (/DMA in) from U5B pin 12. F/F is reset by SC1 through D9, R3; or by /WAIT through R3 and /WAIT line from header pin 29. It's clocked by /EF4. This flip flop could be rewired for other uses, and header pin 29 available for other uses, such as a 1-bit latch, or interrupt latch.

disable power control: Remove D11, C5, C4. These are redundant. If 1804 in use, drill out shorting hold "O" which shorts CPU socket pins 40 and 16, it's also redundant.

disable WAIT, use for IN5 enable Disconnect CPU socket pin 2 (/WAIT) as redundant. Header pin 29 (/WAIT) can be used to gate INP5 when IN5 instruction active. (U6 is logic buffer, not a "latch".)

disable CLEAR: Disconnect CPU socket pin 3 (/CLEAR) as redundant. Header pin 28 (/CLEAR) is available for other use. Components C2, R4, R6 not needed or can be used with the line for other purposes.

possible use of SC0: Header lines as available could be connected to CPU socket pin 6 (SC0) which is otherwise not accessable.

On the processor board:

RAM address in lower memory: Details of the ROM addressing may be tricky. But as 1802 uses page 0 space for reset, interrupt, and special addressing, RAM should be in low memory.

This page and edited content is copyright Herb Johnson (c) 2022. Contact Herb at, an email address is available on that page..