Intel Intellect bus

Last updated Oct 21 2008. Herb Johnson

The following was read off from a 1973 Intel schematic from their 8008 development system called the "Intellec 8". This used a pre-Multibus based bus of 100 pins. Of course it was before the "S-100" bus as it was before the 8080!

Intellec 8 bus from 8008 reference manual

MDB = memory data bus; MAD = memory address bus; phase 1, 2 = clock
DB = data bus out; MDI = memory data in;
IN = input port data in; T40-T47/ = Register/Flag DATA OUT II = interrupt instruction port in;

01 T2/
02 DB OUT/
03 GND
04 GND
05 INT ACK/
06 STACK CYCLE/ (8080 ONLY)
07 SYNCA/
08 T47/ REG/FLG DATA OUT
09 INT REC LTH/
10 T1/
11 MAD 0 ADR BUS LO
12 MAD 1 ADR BUS LO
13 MAD 2 ADR BUS LO
14 MAD 3 ADR BUS LO
15 MAD 4 ADR BUS LO
16 MAD 5 ADR BUS LO
17 MAD 6 ADR BUS LO
18 MAD 7 ADR BUS LO
19 MAD 8 ADR BUS HI
20 MAD 9 ADR BUS HI
21 WAIT REQ/
22 DB IN/
23 MDI0 MEM DATA IN
24 DB 0 DATA BUS OUT
25 MDI1 MEM DATA IN
26 DB 1 DATA BUS OUT
27 MDI3 MEM DATA IN
28 DB 3 DATA BUS OUT
29 MDI2 MEM DATA IN
30 DB 2 DATA BUS OUT
31 MDI5 MEM DATA IN
32 DB 5 DATA BUS OUT
33 MDI4 MEM DATA IN
34 DB 4 DATA BUS OUT
35 MDI7 MEM DATA IN
36 DB 7 DATA BUS OUT
37 MDI6 MEM DATA IN
38 DB 6 DATA BUS OUT
39 T41/ REG/FLG DATA OUT
40 T40/ REG/FLG DATA OUT
41 T42/ REG/FLG DATA OUT
42 INT REQ/
43 -9v
44 -9v
45 T43/ REG/FLG DATA OUT
46 HOLD ACK/
47 -12v
48 -12v
49 +12v
50 +12v

51 HOLD REQ/
52 RESET/ (8080 ONLY)
53 BUS BUSY/ (DA CTL)
54 I/O OUT/
55 OSC
56 HLD INT REQ/
57 IN JAM ENBL/
58 MEM WRITER CYCLE/
59 MAD 13 ADR BUS HI
60 MAD 12 ADR BUS HI
61 WAIT ACK/
62 HALT ACK/
63 T3/
64 I/O CYCLE/
65 MAD 15 ADR BUS HI
66 MAD 14 ADR BUS HI
67 MEM READ CYCLE/
68 FETCH CYCLE/
69 II0 INT INST PORT
70 IN0 INPUT PORT DATA
71 II1
72 IN1
73 II3
74 INT DSBL/ (8080 ONLY)
75 INT CYCLE/
76 IN3
77 II2
78 IN2
79 IN5
80 II4
81 IN6
82 I/O IN/
83 II5
84 IN4
85 II6
86 IN7
87 II7
88 T3A/
89 phase 2
90 T44/ REG/FLG DATA OUT
91 T45/ REG/FLG DATA OUT
92 T46/ REG/FLG DATA OUT
93 RAM MOD ENBL (MEM CTL)
94 MAD 11 ADR BUS HI
95 R/W
96 MAD 10 ADR BUS HI
97 PROM MOD ENBL (MEM CTL)
98 phase 1
99 +5v
00 +5v

Copyright © 2008 Herb Johnson