Kipp Feb 2016 DPS-1 board images
updated by Kipp Feb 28 2016
corrected to use manual's descriptions, with comments Mar 5 2016

CPU Z80 II no rev

Appears your CPU is set for standard operation as per p55 of CPU manual
with front panel support (JJ3 = B-C) except ROM settings

J1  open
JA1 A-B  2732 PROM (error in manual was 2708)
JA2 A-B  2732 PROM (ditto)
JB1 A-B  A15 = 1
JB2 A-B  A14 = 1
JB3 A-B  A13 = 1
JB4 A-B  A12 = 1
JB5 B-C  PROM A11 = 0
JB6 B-C  PROM A10 = 0
JC1 A-B  $ std. addr trans don't care
JC2 B-C  $ std. addr trans don't care
JC3 A-B  $ std. addr trans don't care
JC4 B-C   mem mgmt dont care, $ std. addr trans
JC5 B-C   mem mgmt dont care
JC6 A-B   mem mgmt translator disabled
JD1 A-B $ JD1-6 standard E0 I/O address   
JD2 A-B $   
JD3 A-B $   
JD4 B-C $   
JD5 B-C $   
JD6 B-C $   
JE1 A    
JE2 A    
JF  B-C  $ local intr contrller accept
JG  A-B  $ 4MHz
JH1 B-C  $ full latch
JH2 A-B  $ M1 1 wait
JH3 B-C  $ mem no wait
JH4 B-C  $ I/O no wait
JH5 A-B  $ EPROM 1 wait
JI  B-C  $ local intr controller assert
JJ1 B-C  $ no EPROM, no jmp
JJ2 A-B  $ VI enab
JJ3 B-C    bus strobes enabled with front panel <--
JJ4 A-B
JK  A-B  $ no EPROM, no jmp
JL  A-B
JM  A-B 
JN  A-B  NMI to NMI
JO  B-C  WWRT disabled (it's on front panel)

Floppy Kipp DCB II IA 2020 no  rev 

appears to be as standard setup per page 19 of hardware manual 
2708 PROM on board. 8" floppy drives

J1  1A-B, 2A-B
J2  B-C (PROM 1 wait)
J3  1-15,4-14,5-12,8-11 (2 X 9 pin header, see manual for numbering)
J4A A-B
J4B A-B
J4C B-C
J4D A-B
J5  A-B
J6  B-C
J7  B-C
J8  B-C
J9  B-C
J10 A-B
J11 A-B
J12 A-B
J13 B-C  
J14 A-B
J15 all B-C
J16 A8-A9 (no interrupts, jumper storage position)
J17 row 2-3
J18 row 1-2
J19 all B-C
J20 B-C (16 bit addr)
J21 All B-C (EPROM addr = 0000H)

memory kipp IA-2030 64K 
pay attention to jumper designations in manual

Set per CPU type 5 in documentation, except J19

(CPU=5 is Z80 II, extended addr, M1 Wait On CPU, full latch mode, IEEE mode,
4116, 64K, 8 bit. J19 in docs is B for 24-bit addr, Kipp has A for 16-bit addr)

J1 A-B  
J2 B-C
J3 no jumpers , PC board has trace from A-B
J4 no jumpers, PC board has trace from A-B
J5 B-C  
J6 A-B  
J7 B-C
J8 jumper C
J9 jumper D
J10 top = B, J10 bottom = C
J11 A-B
J12 top = A, J12 bottom = C
J13  top = B,  next = E,   next = G,  bottom = I
J14 A-B
J15 A-B
J16 open
SW1 all switches closed?? (All banks enabled)
J17 C 
J18 A
J19 A (16-bit addr)
J20 B (decodes front panel deposit A = xRDY & MWRITE, B=DBIN & MWRITE)
SW2 all switches closed (unused as J19 = A)

Serial Kipp I/O IA-1190 rev A 

J1 - header as active current loop  
J2 - header as active current loop  
J3-0 B-C (non inverted)
J3-1 B-C
J3-2 B-C
J3-3 B-C
J3-4 B-C
J3-5 B-C
J3-6 B-C
J3-7 B-C 
J4, J5 are parallel port  
J4-1 open  
J4-2 B-C
J4-3 A-B
J4-4 B-C
J4-5 open  
J4-6 A-B
J5-1 open  
J5-2 B-C
J5-3 A-B
J5-4 B-C
J5-5 open  
J5-6 A-B
SW1 - lines on parallel port see manual
J6 set as cascades interrupt controllers, A high pri
J61 A-B
J62 A-B
J63 B-C <---not described in manual
J64 J64A to J63A 
J7- V2A to center
J8A is RS  (port A RS-232)
J8B is RS  (port B RS-232)
J9 A,B to 1 from top (par port B to irq0)
   C,D to 2 (par port A to irq1)
   E to 3 (ser port A txempty to irq2)
   F to 4 (ser port A rxrdy to irq3)
   G to 5 (ser port A txrdy to irq4)
   H to 6 (ser port B txrdy to irq5)
   I to 7 (ser port B rxrdy to irq6)
   J to 8 (ser port B txrdy to irq7)
J10 + to center post           
    W to 0   (no wait states)
J11 7 to -, 6 to - 5 to -, (address 00H, I/O mapped 8-bit)
    M to -, X to -
J12 all open
J13 in manual & schematic not on rev A board, Rev B bet. U20 and U21)