Note about the operation of COSMAC 1802 DIS and RET interrupt instructions. Herb Johnson Mar 3 2016. Exerpts from the RCA USer's manual MPM-201B are lightly edited quotes with edits in []'s. See the Web page below for more details and background, including discussion of Tom Crawford's RCABUG. http://www.retrotechnology.com/memship/rcabug_scrt.html p 40 forward ------------- Interrupt and Subroutine Handling ...When a [hardware] interrupt occurs, it is necessary to save the current configuration of the machine by storing X and P, and to set X and P to new values for the interrup service program. The interrupt forces X and P to be automatically transferred into a temporary register T (P into the lower 4 bits, X into the higher 4 bits), and forces a value of 1 into P and 2 into X, ...and resetting the interrupt enable flip flop E to 0.... [See the manual for SAVE and MARK operations which also act on T, X and P. SAV stores T and MARK sets T, among other effects.] RET: RETURN instruction ... The values in X and P are replaced by the memory byte address by R(X) and R(X) is incremented by 1. The 1-bit IE flip-flop is set [to 1]. DIS: DISABLE instruction ... an instruction similar to RET is executed, except IE is reset [to 0]. While IE=0, the interrupt line is ignored by theprocessor. P 49-50 ------- When X=P: The OUTPUT instructions, the RETURN instruction and the DISABLE instruction. Because each of these instructions increments the RX register, when X=P the RP/RX register will be incremented once for the fetch cycle and once for the execute cycle when it acts as RX. As a result, the byte immediately following the instruction byte is the operand byte. For example, if P=3, the sequence below will output the byte AD by means of the data bus: E3 SEX R3 ;set X = 3 61 OUT 1 ;output byte from memory! AD DB 0ADH ; AD is output on data bus decoded by OUT=1 ... ; next instruction RET and DIS: Because the interrupt mechanism stores X and P in the temporary register T and is typically followed by the exectution of SAV instructions, M(r2) contains the the value of X and P at the time of interrupt. The DIS and RET instructions are used to restore the machine status X, P from M(R2) and give control back to R(P) [ the program counter]. The DIS instruction also resets the interrupt enable flip-flop IE to 0, while RET sets IE to 1. Thus a return from an interrupt program or subroutine may be made with either interrput processing enabled or disabled. NOte that because interrupt is not sampled during the first instruction, the programmer is able to place the DIS 71 instruction in the first memory locatin followed by the byte 00. The net effect is to inhibit intgerrupts until the service routine is set up. p 64-66 ------- Upon completion [of the interrupt handler], return housekeeping must be performed. The contents of registers saved on the stack are now restored. in the example Fig 76, program execution branches to 0053 (the RET instruction which preceeds the interupt handler). The RETURN instruction 70 sets IE-1 and restores the original, interrupted X and P register values. The next instruction executed will be the one which would have been executed had no interrupt occurred, (unless the interrupt is still present, in which case the whole process is repeated). Note that R1 [the interrupt program counter register] is left pointing at 0054 [the address of the interrupt handler] and R2 is pointing at 00F0 as they were before the interrupt. When IE is reset to 0 by the [processor's] 3 interrupt response cycle, further interrupts are inhibited regardless of the /INTER line state. This setting prevents a second interrupt response from occuring while an interupt is being processed. The instruction RETURN 70 that restores original program execution at the end of the interrupt routine, sets IE=1 so that subsequent interrupts are permitted. Sometimes the programmer needs to control IE directly. For example, to permit new interrupts to interrupt the serviceing of old interrupts. Or he may want to shut off interrupts during a critical part of [a program]. The RETURN and DISABLE instructions can be used to set or reset IE without changing P [program counter] and performing a branch. A convenient method is to set X equal to the current P value and the perform the RETURN 70 or DISABLE 71 instruction, using the desired X, P for the immediate byte. For example, if IE=0, X=5 and P=3, the sequence ;program counter is R3 E3 SEX R3 ; set X to R3 70 RET ;return X to R5, P to R3, 1-IE, R3=R3+1 DB 53H ; forces X=5 P=3 - which is no change ..would have no effect other than setting the interupt enable IE. A similar sequence with a 71 instruction can be used to disable interrupts during a critical instruction sequence. ------------------------------------------------------------------- Note from Herb: Here's an example of how RCABUG's restores interrupts at the end of the SCRT return routine: SEX R5 RET ; PERMIT INTERRUPTS DB $25 BR EXITR ; BRANCH TO EXITR. ... EXITR SEP R3 The SEX R5 instruction sets X to 5; P is already R5 the standard "call" program counter. Thus when RET is executed, X is incremented *during the execution* and uses "25" as its operand. So X is set to 2 (R2 becomes stack pointer again) and P is set to 5 (program counter is R5, no change) and the next instruction after the now-skipped DB is executed; the branch to leave the subroutine return by setting the program counter to R3. The same sequence occurs in the "call" subroutine support code, only SEX R4 / RET / DB 24 is used because R4 is the standard "return" program counter in that code.