This page last updated May 14 2023. Copyright (c) 2023 Herb Johnson all rights reserved
In March-April 2004 there was a discussion of S-100 bus termination in the comp.os.cpm Usenet newsgroup or discussion group. Use Google.com or other portals to access Usenet archives. I had further discussions and notes, and with permission I gathered the comments and notes on this Web page. I've also gathered other resources over time. They are as listed below. - Herb Johnson
S-100 bus termination, discussion 2004
Bus theory and measurements
Someone built a terminator card on a S-100 protoboard, based on the Compupro Active Terminator. REad Nick Papadonis's construction notes on this linked page.
In Feb 2021, I had a conversation with a former MITS/Pertec system service tech. They informed me about some interesting problems with the MITS Pertec S-100 backplane and connectors. Apparently the connectors became intermittant due to stresses produced by screwing the "ears" of the connector into the chassis and backplane board. Read their conversation for details.
See other S-100 pages on my Web site for more information.
See this Web page on S-100 traditional power supplies.
Summary:: In March-April 2004 there was a discussion of S-100 bus termination in the comp.os.cpm Usenet newsgroup or discussion group. See Google.com or other portals to access Usenet archives. The notes below are a summary of that discussion, responses by others, and exerpts from S-100 manuals and other documents on bus termination issues and products. I've recieved permission from the correspondents to exerpt their posted correspondence. I've also recieved private correspondence which is published here. I'll be glad to add links and make corrections to this document when requested. If you don't know what "S-100" means (or means to me), start with my S-100 Web page. - Herb Johnson]
discussion of S-100 bus problems on comp.os.cpm:
In March 2004, Thom Fischer mentioned S-100 bus termination on comp.os.com. This is a traditional problem in any bus-based computer, whether minicomputer or microcomputer. It was recognized as a problem in S-100 systems as soon as cards ran faster than a few MHz and on a bus of more than a few inches long. It was mentioned in a generic way in the IEEE-696 specification. A related problem in the S-100 world was/is repair and test of cards on a "bus extender", literally a card that extends the S-100 bus above the card cage, so you can work on a card "on" the bus. I remember any number of problems with cards, which would work on an extender card but not back in the cage (or vice versa).
Since TTL & LSTTL chips- the "logic" devices that were and are in use with S-100 systems - respond to signals and glitches (unintended signals) up beyond several MHz, even a "slow" S-100 system built from TTL chips will have problems from events or mistiming or noise at those speeds. Proper termination of signal lines reduces noise and improves signals. But engineers of the 1980's had a range of opinions as to how to achieve "proper" termination, taking various factors into consideration, and so many termination designs were developed for the S-100 bus.
As Fischer suggested in his posts, an "active" terminator is superior to "passive" resistor-only termination. Active termination means the terminating network is powered by a stable voltage source, such as that 2.7V in the IEEE spec. A passive termination is resistors only, but these always draw power from the +5V supply: that adds up across 90+ lines. Chuck Falconer responded to Tom Fischer's post with a generic R/C dynamic termination design: a series resistor and capacitor to ground, and a 10K ohm pull-up, per line. This only draws current during signal transitions and so draws less power. It also responds faster to high frequency signals than a resistor-only design and so requires careful selection of that R-C combination for correct frequency response. Check the manual notes on the CCS terminator design below for more discussion of passive, active and dynamic termination.
Thom Fischer's proposed solution to bus problems with legacy cards includes use of a bus driver product from Texas Instruments which uses a special CMOS bus driver scheme that manages the bus during bus transitions. Lee Hart, Howard Harte, and others discussed the merits of CMOS vs. TTL, of substitution of various logic families on old TTL-based boards, diode clamping. Exerpts of those discussions are below, with Web links where appropriate. Howard Harte offered some previous results from bus testing, and as of early April 2004 promised to post subsequent testing.
I [Herb Johnson] have provided in this document some description of technical terminology for those not familiar with capacitance and inductance as considerations in bus and digital logic. I have also included in exerpts from two S-100 manuals of bus termination products; and documents sent to me personally. Harte's posting of actual test results are in a seperate section of this document for clarity. It's a challenge to edit a branching discussion thread into a linear document; any errors due to context or sequence are of course mine and I encourage any corrections. When I use extensive quotes or exchanges from the discussion thread, I'll use itallic text to make it clear who authored the comments.
Edited by Herb Johnson
Here's a portion of Thomas Fischer's early posts from the thread "Subject: S100 buss termination was Re: 16C550 help request":
When Howard and I originally defined bus termination for the EXP-9AT (S-100) we unabashedly copied Bill Godbout's (and George Morrow's) scheme of an adjustable buffered voltage source (2.3-2.9 volts) feeding the individual termination resistors along the backplane. What became an issue in testing various legacy board configurations was sensitivity to variations of the termination source voltage (arbitrarily 2.7 volts). Additionally, we found that Morrow's Wunderbuss (which I once second-sourced as an option for the original IMSAI 8080 back in 1979-1983) varied with termination resistors ranging from 190-510 ohms, as did Godbout/CompuPro/Viasys motherboards from 1979 through 1986.
What really surprised us was Godbout's use of two paralleled 1500 ohm resistors in motherboards of 1985 vintage. We speculated on various reasons WHY, but no clear answer came. When you and another customer with identical board sets (but differing termination schemes; the other fellow is using a Morrow Wunderbuss) ended up requiring differing "flavors" of Lattice timing code to make the Super I/O board function properly, Howard began to do some exhaustive emulation and testing with his HP 16500C Logic Analyzer of the S-100 signals.
His conclusions ultimately led to our abandonement of the old termination scheme designed into the EXP-9AT, and adoption of the "weak latch" logic suggested by TI. The beauty of the TI approach is that you only need a single device from their logic family on the bus to achieve the latching. Additional devices in parallel apparently don't affect the latching or loading in any material way. We first thought of using the TI device family as buffers on the Super I/O and MPU-C, but since we had always considered offering the EXP-9AT motherboard as a stand-alone product, the revised design now utilizes the TI parts in all active S-100 bus lines (excepting the open-collector signals). Howard is testing and pushing the S-100 bus speed ever higher to see where the present ceiling is. Things can only get better!
After some posted replies regarding bus speed and legacy solutions to bus termination, Thomas responded: "It's my understanding that by the time Godbout's company had morphed into the "Viasyn" brand, bus speeds of about 10 MHz had been reached. I've always wanted to talk with Mark Garetz about the transition, but the other significant factor is that they did away with (S-100) on-board voltage regulation and ran fully regulated supply voltages directly from the bus. This perhaps lowered the source impedance of the supply voltage and improved noise immunity to some extent. Howard has found that by replacing original linear regulators, like the ubiquitous 7805, with modern low dropout equivalents (some with higher current capabilities to boot!), that performance of legacy i.e. 1976-1983-era boards improved noticeably.
Our focus with the IMSAI Series Two development is to allow as much support as practical for users of these older boards, and to provide a platform that is more forgiving and capable of higher speeds. The constant voltage source/series resistor shceme that was widely practiced (but mutated to extremes) seemed to have been arbitrarily tailored to make the best of each manufacturer's performance, ergo, deviation from "the standard". IMSAI used a 220/330 ohm termination scheme in the second generation systems including the VDP and PCS lines. We found that even then (1977) placement of individual boards on the bus often made for greater or lesser reliability in the system. This was frustrating for more than a few. In essence, it was "alchemy" at best.... I strongly encourage fellow designers and enthusiasts to read the link to TI's site referred to in my previous post.
-Thomas "Todd" Fischer
Early in discussion of bus termination was an issue of the "speed" of the bus. That's a loose term but generally it refers to the clock speed of the master processor card, usually the clock speed of the only microprocessor. If you run the bus "slower", you generate less crosstalk. Also related to speed is the type of hardware you use; old TTL, LSTTL (lower power and Schocky noise margins), CMOS, etc. These were also discussed in the disucussion thread during late March 2004.
Lee Hart mentioned that he designed an 8MHz Z80/8086 system that was obliged to use legacy 2MHz memory. His solution: change the processor clock speed when it accessed memory! He explained: "I just meant I could use exactly the same bus drivers/receivers as the original 2 MHz design (74LS parts), and run the Z80 at the same clock frequency (2 MHz) for all bus accesses. Thus all legacy boards worked exactly the same, with timing and rise/fall times all identical. But when the CPU accessed memory or I/O on the CPU board itself, it could run at 8 MHz without wait states."
Lee continued: "The problem with wait states was that the timing of a memory or I/O access with wait states is *not* the same as it would be with a slower clock speed. With wait states, the sequence of events takes place much faster, but with a pause inserted at one particular point. With the slower clock speed, the entire access cycle is stretched out. Softer bus drivers can be used, which produce less ringing and noise on the bus."
Lee Hart also refered back to comments about a buss as having characteristics of an antenna or transmission line: that is distributed capacitance, inductance, and coupling of signals from one line to another. "You may want to study up a bit on transmission line theory to understand what is causing the noise and ringing on a bus, and what can be done about it. It's not alchemy [a reference to Fischer's earlier comments]."
Lee said: "The problem with legacy S-100 cards is that they weren't always designed by people who knew anything about transmission lines, either. The loading of the 'stub' (wire from edge connector to the IC used on the card) on each card has an unknown length and width, and the IC used is unknown. This means reflections and noise are inevitable if you have fast rise/fall times and high clock frequencies. That's why I think you may want to look at deliberately soft rise/fall times, and slowing down the processor clock instead of depending on wait states to deal with legacy cards. Once rise/fall times are slow enough, the ringing and noise disappears." [Slower clock rates don't necessarily mean slower rise and fall times however. - Herb]
Thomas Fischer responded: "My point was simply that no single or specific approach to previous termination schemes solved problems for more than a handfull of boards in years past. Undeniably, the problem is one of transmission line theory, which yielded such wide-ranging results with a small change of any single value, that to take all of these variables and try to bring them together as a bus standard capable of greater speed and performance was seemingly doomed from the outset. Many of us didn't know any better and kept plodding forward, implementing those "tweaks" that gave us the best performance. The device manufacturers weren't of much help, with a few notable exceptions like Analog Devices and National. Simply changing older pin-equivalent devices with later logic families often opens an entirely new kettle of fish." Fischer noted his associates were measuring signals from actual legacy S-100 cards in use. He plans to show that work and results from his plans to use the TI CMOS "weak latch" technology to improve bus performance.
Discussion continued with considration of old vs. new chip technology, as well as the characteristics of bus operation at speed. Thomas Fischer's reference to solving these problems as "alchemy" rung true to many correspondents. Randy McLaughlin posted: "[If] I understand what is meant by alchemy, it is. Once you try and interface to a few different boards from as many manufacturers deciding what timing to use and how to reduce noise and ringing is pure alchemy. Until recently there was no solid way to handle many of the problems. The [TI CMOS] latched drivers handle many problems inherent in legacy systems.
Randy continues: "No matter how well the developer of an S100 board understood transmission line theory there has always been multiple ways of handling it and since everyone chose their own methods conflicts are inevitable. I have S100 equipment that runs from 2mhz to 8mhz from at least a dozen manufacturers and I can swear that no matter how good the manufacturer is it is a crap shoot to know what will work with what.
Lee Hart responded:" I think I understand what you are saying. If you don't understand transmission line theory, then buss termination all looks like magic. You can still try various solutions by trial-and-error, and might get lucky and make it work. But, it's still all magic.
"If you do understand transmission line theory, then you know what's going on and know what can be done about it. But you *still* might not be able to actually fix the problem. For example, the problem may be so complicated that the "optimal" solution cannot be implemented.
"Well, I *think* I understand transmission line theory. But I can't see how these latched drivers will be more than one more option in the designer's "bag of tricks". They will help in certain cases, but hurt in other certain cases.
"In particular, they will help when the problem is that there are times when no driver is driving the bus, and during these times, noise from other lines is causing this line to bounce around, and there are receivers on that line that will act on the noise as if it were a signal. But they will make matters worse when there is a driver on that line, because the latch's high/low state becomes another source of noise being added to that bus line.
"Another concern is that the newer chips use smaller, faster geometries. Their outputs have sharper rise/fall times. This will also make matters worse. A 12" bus length is no problem for an old 74xx TTL chip; of minor concern to a 74LSxx chip, but murder on a 74Sxx chip. The newest parts are so fast that you have to use transmission line designs even for very short traces within one board. And, you need one heck of a good oscilloscope to even see the edges and ringing that are causing the problems.
"You might want to try this with your latched driver chips. Hang just a long piece of wire onto an output. As you make the wire longer, observe this output as you pulse the line low. At some length, the driver will probably break into sustained oscillation. The output of the latch goes high; the high travels down the wire, bounces off the open-circuited end as a low, hits the latch and triggers it low; this low now travels down the wire, bounces back as a high, and the cycle repeats.
"As you connect things to that wire, you add more capacitance and inductance to it. So, the maximum length at which it can sustain this kind of oscillation gets shorter. You get in trouble when the max length starts getting close to the actual bus length!"
Lee Hart emailed me privately a basic description of transmission lines as they relate to digital bus lines. I've put it in my reference section. - Herb
In Thomas Fischer's discussion, he references his product's use of TI CMOS chips which use "weak latching", a method used by Texas Instruments in their design of some CMOS logic devices. TI discussed this method in an application report "Bus-Hold Circuit", SCLA015 of Feb 2001. It can be found at http://focus.ti.com/lit/an/scla015/scla015.pdf In this note, TI refers to a "novel bus hold circuit" to deal with three-state drivers which otherwise leave the bus line in an undefined logic state. TI's note describes bus lines as transmission lines (i.e. capacitance and inductance), reviews some practices, and describes its proposed driver solution.
A few people reviewed the TI document and reported their opinions. Randy McLaughlin noted his hardware experience is modest but said: "At least I appreciate the fact that TI answer is simple. The latching drivers sense the current state of the buss and attempt to keep it there until the buss has enough current applied to pull it up or removed to pull it down that it latches at the new state. This reduces ringing especially in the small amount of time that the signals are tri-stated and would normally be floating. This also effectively stretches the data stable window further and may help on say a memory write where the memory card may still be reading the buss while the CPU could be so fast as to otherwise have left the data lines floating."
Dwight Kelvey replied: "Actually, these type of termination can increase both cross talk and ringing. The part that makes them work well is that they move these nasty parts of the signal away from the thresholds of receiving devices. There is no free lunch on transmission lines. Energy put into the line will propagate. If it is added at the end by a latching device, that signal will be sent down the line as well. Even a float by [tri-]stating an output is a signal ( as anyone who works with DDR RAMs soon learns )."
"The difficulty with the TI feedback devices is that they add additional energy to the line that ends up causing the input protection devices to absorb the extra current, some place else. This may be OK for receiving devices that are intended to handle over and under voltage but the general logic device, that is normally used on older S-100 boards, are not designed to take these as continuous loads. This shortens the life of these devices by stressing them in ways they were not intended."
Dwight continues: "The safest termination is to terminate at both ends. If there is excess cross talk, it is often easier to deal with this by placing addition series resistance with the source [driver]. This slows the rise time of the signal. On an existing machine, this can be done with a small card between the original card and the buss."
Lee Hart had this exchange with Howard Harte about the TI chip solution:
Lee Hart:However, I'm not sure that propagation delays are the issue for bus noise. What I see happening is that the S-100 bus was designed for old slow TTL, and isn't suited for modern high-speed logic. If you just substitute faster chips (74LS --> 74S --> 74ABT etc.), the speed of the rising and falling edges are so sharp that they generate lots more ringing and noise. And, the faster chips are capable of *responding* to this noise as if it were signals.
Howard Harte says: The Super-I/O uses 74ABT CMOS bus drivers with propagation delays in the range of <3ns, and high output drive. They are sensitive to slow rise/fall times, [so] floating or high-Z inputs on the S-100 bus can put these drivers into oscillation...
Lee: This is kind of a design problem with the TI chip; it is not suitable for long, noisy buses. Can you try changing it back to an earlier, slower part? I have had very good luck with 74HC. Their output rise/fall times are far softer, producing far less noise on the bus. Yet their propagation delay is still relatively fast.
Howard Harte also posted: "I am hoping that some of the TI bus termination circuits can help this problem, as they include the "weak latch" to hold signals at their last driven state [and] they include diodes that clamp over/undershoot to VCC/GND.
Lee replied:" Of course, there are lots of solutions to every problem. I think TI has decided to invent a new problem, for which they have a solution to sell you. :-) That's not to say it isn't a viable design option. But the more normal solution is to have terminating resistors to pull a tri-stated bus to a defined logical state. You need them anyway to terminate a long, high-speed bus. And if there is so much noise that the terminating resistors can't control it, then you have *other* problems to fix!
Howard Harte's response: "I just wanted to mention that many parts employ the "weak latch" scheme to control floating inputs. For example, besides the 74ABTH series from TI, the Lattice CPLDs have a couple really nice features on the I/O pins which are user-selectable: slew-rate control (fast/slow,) output drive capability, and choice of "pull-up," "bus friendly" (ie, weak latch) and nothing on the inputs. I also want to point out that some devices drive their outputs to the inactive state before tri-stating, so, for example, an address bus could be driven to 0xFFFF just before the address outputs are tri- stated. I also believe that PCI uses the "weak latch" scheme.
Some time later, Randy McLaughlin posted: Howard sent me 74abth245's to use on my SuperIO. I was having problems with some of my CPU's before. Now they all work flawlessly. Howard had spent a huge amount of time tweaking the timing of the CPLD to match to one CPU or another but matching all looked like it was out of the question. Howard had appeared to be resigned to having different CPLD code for particular CPU's. Now I am not so sure, these new driver chips may handle many problems themselves. FWIW the 74abth products appear to do a wonderful job." - Randy
Todd Fischer described their new IMSAI motherboard: When Howard and I worked out the layout for the EXP-9AT (Active Termination) motherboard (standard IMSAI form factor, but 9 slots and 7" deep), we incorporated relatively narrow bus traces to reduce reactive coupling between lines, as well as a "guard band" ground trace between bus traces. We've used ample "copper pour" to increase the effective capacitive coupling between power and ground layers as well... kind of like adding multiple parallel capacitors for additional filtering. The low impedance power feeds are as generous with copper as reasonable practice would allow. Nothing especially new here; just a matter of using our best judgement after evaluating many earlier legacy motherboards that have yielded higher-than-normal performance during our testing. --Thomas "Todd" Fischer
Michael Mahon responded to earlier termination discussions: "Anyone who thinks that hard (low-impedance) clamping a bus is the solution to a problem should contemplate that a forward- biased diode reflects the incident pulse inverted, like any lower- than-characteristic impedance.
"Nonlinear impedances on a bus are the cause of many ringing problems. Of course, the structure of most ICs dictates that inputs (and outputs) remain between ground and Vcc, but this should be accomplished by good termination, not by clamping.
"The problem with the relatively uncontrolled S-100 bus is that many of the cards that plug into it are not designed to handle high speed signals (I wonder why? ;-), and so attempting to use the bus with fast signals can be expected to create ringing problems that are not easily solved with any simple termination scheme.
"Slew-rate-limited bus drivers go a long way to minimizing the problem, but _all_ the drivers that drive the bus must conform to the slew rate limits for it to be effective. Since the usual objective for using an S-100 bus is to allow lots of pre-existing cards to be plugged in, the best solution is usually impractical." - Michael
Additionally, in regards to Howard's reference to PCI bus, Michael noted: ..in that case it is usually called "incident wave" signalling, in which the _first_ thing that the bus line does is considered to be the signal and any subsequent wiggles are ignored. The problem with such schemes is limiting the response to the setup and hold times suggested by the bus clock. -michael
The discussion made some references to overshoot and undershoot, and the use of diodes to limit those effects. I have some further notes on diode termination using Schottky diodes in another section of this note. - Herb
The early S-100 bus cards used eight-volt unregulated power to supply cards with on-board five-volt regulators. Later cards were used with no regulators on a five-volt regulated bus. Some comments about replacing voltage regulators led to a discussion of the virtues and problems on on-board regulation and a 5V bus voltage. - Herb
Fischer noted: Howard [Harte] has found that by replacing original linear [on-board voltage] regulators, like the ubiquitous 7805, with modern low dropout equivalents (some with higher current capabilities to boot!), that performance of legacy i.e. 1976-1983-era boards improved noticeably."
Herb Johnson replied: In my own S-100 repairs, I've noted that simply replacing old voltage regulators with less old but identical regulators, cards have also worked better! Some Cromemco 2MHz & 4MHz Z80 cards which did not work were "fixed" by this repair. My impression is that the regulators lose their ability to regulate over time.
Allison posted: If you remove [the regulator and change the bus to 5 volts] then the BUS voltage MUST be well regulated as cables and PC traces have resistance. I've seen a volt of voltage sag from one end to the other of a typical 18 slot S100 bus with 16 cards in it pulling 20A. So if you start anywhere on that bus at 5V... somewhere you going to be hurting for power. Typical TTL wants to be within 10% of 5V and some MOS-LSI will tolerate only 5%, off spec parts or parts with poor cooling may be fussier.
Randy McLaughlin noted: ....I talked to Howard about the power supply on the IMSAI series two. I said it would be a good idea to eliminate the power booster and go with just the +5v & +/-12v as on the later CompuPro (Godbout/Viasyn). He said [Fischer-Freitas] preferred to stick with the +8v & +/-16v to keep it compatible with older systems.
My two cents is offer an option to have it with or without the power booster. If you use the lower voltages the signals will be cleaner, the boards will be cooler, and there will be less to fail. An added benefit is that with cooler boards they will last longer. - Randy
Herb Johnson commented: Thom's and Harte's experience with replacing voltage regulators with modern ones may be as described. But I've found that replacing really old regulators with just "old" regulators was also an effective repair. I believe that these regulators just wear out over time and become less able to regulate.
Also replacing the tantalum bypass caps associated with these regulators is a good repair. Caps also fail over time and an open cap will not filter noise very well. (A shorted tantalum cap will explode and burn and become both open and obvious for repair.) Cromemco Z80 processor cards, in my experience, may work again just by replacing the 5V regulator.
Randy, I believe the isolated on board regulators also help to isolate cards from noise over the power lines of the bus. Large current swings can generate large cross coupling; the old 8V to 5V regulation may provide some buffering of those swings. I look forward to Harte & Fischer's report of bus activity, maybe they will cover these events as well. - Herb Johnson
Randy replied: I agree that if you remove the voltage regulators and the filter caps it is not a good idea. By leaving the filter caps where they were both before and after where the regulator was helps. Of course on boards I've had trouble with I've been known to solder filter caps to the bottom of every IC (it can really help).
I have also had a great number of caps blow up on me. Just a couple of weeks ago a shorted cap damaged my MacroTech Dual processor card :-(. Tantalums are the worst. I've seen plenty of caps die and they can be spectacular to watch while at the same time bring tears to your eyes.
The regulator problem Howard had was on the SuperIO (not an aging problem). I never had any trouble with mine using an older style regulator, but supposedly Howard did. To be safe he sent me a replacement regulator and a replacement tantalum cap. If it was anything it would be the fact that the CPLD he is using is so fast it may have been seeing transients as real data. - Randy
Lee Hart posted alternatives about on-board regulators:
1. You can also leave the 7805 in place, and just short its input and output together. It wastes a few milliamps of supply current to needlessly power the 7805, but is easier that removing the chip, and easier to restore the board to its original configuration if needed.
2. Some S-100 cards did not use the 7805. There were lots of alternative regulator chips, discrete regulators, even simple resistor/zener regulators. Be sure you know what you're doing before shorting what you *think* is a 7805!
3. Today, there are low-dropout 3-terminal regulators that work with just a tenth of a volt or so difference between input and output. I suspect you could replace a 7805 with one of these, and the card would work with either 5v or 8v on its input.
If you want to support legacy S-100 "furnace board" cards that draw a lot of 5v power, then you should keep the on-board 5v regulators. The S-100 bus has only two pins for +8v. At high currents, there is a lot of voltage drop between the power supply and the actual chips on the various boards. The on-board regulators were an attempt to get a solid +5v to the chips despite all these voltage distribution drops. - Lee A. Hart
Randy replied: Many S100 back-planes had multiple places for the PS to connect to. As such it was possible to use heavy external buss lines between them (I don't remember ever seeing it done). More over for the particular back-plane we were referring to is only 9 slots and as such the 6" we are talking about should be short enough to eliminate many of the problems you are referring to.
Most of the really power hungry boards of the earlier S100 systems were the RAM cards. The SuperIO supports 512K of low power 70ns SRAM and those hotties can be left out. - Randy
Lee Hart posted in response to a comment about slowing down the bus: "...in fact that is a common way to deal with it. For example, the address inputs of dynamic RAMs are essentially purely capacitive. It is common to have dozens of RAMs all wired in parallel, spread across a board. If you try to drive them directly with some TTL chip, the sharp rise/fall times, chip capacitance, and inductance of the connecting wires form a resonant circuit, and you get severe ringing and overshoot. So, what you will see on most RAM boards are resistors in series with the outputs of the address driver. The resistors lower the "Q" of the LC circuit so it won't ring or overshoot. These resistors are typically 10-47 ohms. Too small, and they don't damp out the ringing. Too large, and they slow down the address circuit too much.
If applied to the S-100 buss, you would need to put a series resistor right at each driver output before it enters the bus. It would be hard to pick its value, because you don't know the amount of capacitance the various receiver chips and edge connectors would be adding. And with TTL receivers (which draw input current), the series resistor would cause a voltage drop which would worsen noise margins."
In subsequent discussion, Howard M. Harte wrote: "... Since the propagation delay is very short (<3ns) the slew rate is very fast. Changing to a 74LS245 on the data-in (DI) bus driver cleaned up noise on the bus considerably. What we need to do here is some testing. At some point, I will prepare a report with timing diagrams and scope waveforms that show the results of this testing.
Lee Hart responded: "[upgrading bus chips] could be a useful strategy in general. Try substituting older, slower chips for bus drivers and receivers where you can spare a few nanoseconds of propagation delay. As I said, I've had the best luck with 74HC parts (good combination of speed and soft edges). But it's hard to beat old open-collector 74xx parts with a properly terminated bus for ringing-free bus waveforms.
Lee continued:"I ran across an excellent article on bus ringing and noise in a Cypress [Semiconductor] application note. I just sent a [printed] copy to Herb Johnson, and would be happy to send you one as well if you like."
Follow the link above to more information about that Cypress Tech Note and to related notes; and to an example of a Compupro bus calculation of impedance, capacitance and propogation delay. - Herb
Allison noted how several design decisions about S-100 cards affect bus performance: also see her comments on her Northstar systems.
Bus lines are the electrical equivilent of transmission lines. They are modeled and designed the same way. The problem is manifold for the designer [as follows:] TTL (LS,F,S,H and cmos varients) are rotten drivers with differing logic High and logic low output impedances. They are equally rotten line recievers, they do not reasonably load the lines (Transmission lines). Add to that their threshold votages are all over the map (exception is SCHMIDT trigger input devices). MOS input devices don't load the line at all, they do present a capacitance to the line aggravating the problem. Traces going from (or to) the bus connector travel around the [S-100] board extending the bus in odd ways with equally interesting reflections and noise contributions. Local (on card) groundloops inject noise back out onto the bus. Adjacent lines carrying signals, also mismatched radiating their bit of excess noise to their neighbors. This is why S-100 and other less sophisticated busses were sometimes good and other times horrid for reliable systems. - Allison
Howard Harte is testing and developing IEEE-696 products, working with Fischer-Freitas Howard posted on comp.os.cpm in April '04 about his findings from earlier tests on some legacy S-100 cards. As Thomas Fischer originally posted, he and Howard are working on a new IEEE-696 I/O card product for Fischer-Freitas. Howard told me in private email he may have more findings later after additional tests with the TI driver chips. - Herb Johnson
Wow, this turned out to be a good discussion. As others have pointed out, it is not the clock frequency of the S-100 bus that necessarily poses the problem. Gate to gate propagation delay is more the issue. I've overclocked a system here using the Super-I/O with 512K SRAM modification and a Northstar ZPB-A2 CPU card with a 20MHz CMOS Z80 part to 8MHz (16MHz crystal.) This system runs remarkably well using "stock" components such as the N* Horizon motherboard. (Note that the on-motherboard UARTS do not operate properly at 8MHz)
I've observed the following three issues looking at the S-100 bus as specifically related to the Super-I/O, various CPU cards, and certain other memory boards:
1. Local to the Super-I/O card: The Super-I/O uses CMOS logic for the entire board. The bus drivers are 74ABT (Bi-CMOS) with propagation delays in the range of <3ns, and high output drive. Since these drivers are CMOS, they are sensative to slow rise/fall times. See TI datasheets and the TI PDF document "slow and floating CMOS inputs" page 7 for specifics.
Floating or high-Z inputs on the S-100 bus can put these drivers into oscillation, whereby excessive current is drawn from the on-board regulator. This lowers the bus driver's internal reference voltages, which causes this condition to worsen and generate noise on the S-100 bus. I believe that this problem was mitigated by replacing the 7805 regulator with an LT343AT (5.0V, 3A) regulator. Using a four-layer PCB with power and ground planes would probably also help.
2. S-100 bus termination: reflections on the S-100 bus lines are propagated through fast bus drivers as valid transitions. I've seen this for example:
During a read (I've observed this only on I/O reads, but it may also happen for certain memory reads) noise on the data in bus causes a glitch on the S-100 sOUT signal.
I am hoping that some of the TI bus termination circuits can help this problem, as they include the "weak latch" to hold signals at their last driven state, and in addition, they include diodes that clamp over/undershoot to VCC/GND. I believe that these parts will work well on the backplane. In addition, pin-compatible "bus hold" bus drivers are available as "74ABTH245's" which are the ABT series logic with the bus hold feature. These can be utilized on new boards to add to the robustness of the bus, and perhaps to help existing backplanes which do not have termination.
3. I've seen that many CPU cards deviate from the "standard" with regard to timing. Some CPU boards replicate data input on the Data In bus to the Data Out bus, and some don't. Some CPU cards glitch on various S- 100 strobe signals (or perhaps reflections cause the glitching.) Some CPU cards even output the wrong phase of the clock to the S-100 bus.
Certain CPU cards assert PSYNC late in the bus cycle, and some CPU cards "miss" wait-states depending on when RDY is asserted on the bus. I can't remember the details at this time, but I've captured waveforms from various S-100 CPU cards, and annotated some of these anomalies. I have them somewhere here in a PDF if anyone is interested.
Howard Harte (text by permission)
Lee Hart posted discussion referred to a Cypress Tech Note. Lee sent me a copy, of "System Design Considerations When Using Cypress CMOS Circuits". That note dates from Jan 1992, March 1993, and from both 1986 and 1997. It may be in their Applications Handbook, (Aug. 1991). Courtesy of Cypress Semiconductor, I've obtained a PDF document for this note and posted it on my Web site. [Note: as of May 2009 I cannot find it on Cypress's Web site. An aggressive Web search may find copies. - Herb].
In 2004, a Cypress applications staffer also referred me to to other on-line Cypress documents: "In addition, depending on the Cypress device you are using, we have many application notes geared towards specific types of design. Here are a few titles of other good application notes (depending on your system, of course) [in PDF format]. You can find more application notes under each product category listing by visiting http://www.cypress.com". - Cypress Semiconductor.
As of 2021, to obtain copies of these documents, either search the Cypress Web site or use Web search and include "cypress" in the search string. I have copies of some of these. - Herb
using decoupling capacitors - AN1032
Termination and Biasing of HOTLinkII High-Speed Serial I/O - AN1055
High-speed Board Design Guidelines (using CYS25G0101DX as an example) - AN1169
High-Speed Memory Design Techniques - AN4010
System Design Considerations: Board Terminations - AN1062
NoBL SRAMs and Bus Contention - AN1092
SRAM Board Design Guidelines 001-71771
I followed the examples in the Cypress "System Design" tech note to calculate the theoretical impedance, propogation delay and capacitance of a Compupro 21-slot motherboard. By actual measurements, this bus card is 15 inches long and has bus lines of .020 inches width over a "ground plane" of alternate ground lines under and above a .040" circuit board. The Cypress note suggests a trace thickness of .003 inches and a PC board permeability of 5. This data suggests a "micro stripline" impedance of 87 ohms, and a propogation delay of 1.93ns. From fundamental physics, the capacitance between two plates, this same data suggests a bus line capacitance of 37.5pf, considering the lines and circuit board only.
The Cypress note suggests a series RC terminator to bypass high-frequency activity on the bus. For activity that is twice the propogation delay - that is, twice 2ns or four nanoseconds - the series resistance should match the impedance of 87 ohms and the series capacitance should be about 21pf. The new propgation delay of the RC terminated bus would then become 2.45ns, and the new impedance would become 68 ohms.
Lee Hart's reviewed my numbers and responded: "[87 ohms unterminated impedance] sounds correct. It's lower than people would think because of the extra ground traces between pads."
I asked: The propogation delay would be 1.54 ns/foot, or 1.93 ns for the bus. In effect, Lee, is this the frequency (500MHz) at which the characteristic impedance (87 ohms) is manifest?
Lee said: "No; the characteristic impedance is independent of frequency. The 1.93ns is important because it tells you that if you DON'T properly terminate the bus, the reflection will take 2 x 1.93ns = 3.86ns (pulse from a driver travels to far end, bounces back, and arrives back 3.86ns later). If your logic can clock this fast (260 MHz), it will count this ringing as another clock pulse!"
Regarding the theoretical capacitance, Lee added: "[A calculated bus line capacitance of 37.5 pf is] even lower than that in reality, because of all the capacitance of the edge connectors and from the chips connected. From [reading] ham radio magazine articles, they find 30-50 ohms common [in high frequency circuits which drive many inputs]. It can be impossible to terminate it because the driver ICs can't drive this low an impedance. Since the extra capacitance also increases the propagation delay, I also suspect even a 100 MHz flip-flop will malfunction." - Lee Hart
From my private correspondence of April 2004, engineer Lee Hart explains below how any computer bus amounts to a bundle of transmission lines. That's a technical term which relates to the effects of high-frequency electrical activity on relatively long wires. Lee's notes refer to two fundamental electrical components. Inductors are coils which have MORE resistance at high frequency; capacitors are simply metal seperated by insulators, which have LESS resistance at high frequency. Since a bus is a bundle of long wires, each line of the bus acts as a transmission line, which can be modeled by a circuit of inductive, capacitive and resistive components. But a bus line is also a wire which carries DC current, andm ost termination schemes have effects on the DC current through the "drivers" which switch these lines, and therefore the power used by those drivers and the terminators. Lee considers these effects and others in his comments.
Lee's notes are good background reading to interpret the other notes and document exerpts on this Web page. I've edited his comments and published them here with Lee's permission.- Herb Johnson.
A motherboard isn't just a long piece of wire. It acts like a long string of inductors (the traces), with capacitors every so often (the edge connectors)
_ _ _ _ _ _ _ _ _ _ __| | |_____| | |_____| | |_____| | |_____| | |__ L _|_ L _|_ L _|_ L _|_ C ___ C ___ C ___ C ___ | | | | gnd gnd gnd gnd
If you put a perfect square wave into such a network, you get a badly messed up waveform out the other end, with lots of ringing and overshoot.
It turns out that for any values of L and C, there is one value of R that precisely damps out the oscillations. It is called the "characteristic impedance" of the line. You put this resistor at the far end, like this.
VCC | > R1 _ _ _ _ _ _ _ _ _ _ > __|\__| | |_____| | |_____| | |_____| | |_____| | |__| |/ L _|_ L _|_ L _|_ L _|_ L | driver C ___ C ___ C ___ C ___ > R2 IC | | | | > gnd gnd gnd gnd | gnd
It doesn't actually matter to the AC waveforms whether R goes to ground, VCC, to both as two resistors (as shown); or to some DC voltage source. As long as the other end is well-bypassed to ground with capacitors of relatively high value, any of those options are the same as connecting one or both to ground.
So, one termination solution is to make the driver an open-collector device, and connect one resistor of value R to VCC. Another is to use a totem-pole TTL gate for the driver, and split R into two resistors; one to GND and one to VCC, so they form a voltage divider that holds the voltage with the driver tristated about halfway between a logic 'high' and 'low'. The parallel resistance of these resistors needs to be the correct "R" to terminate the bus. This scheme has additional advantages as I'll describe later.
But there is an additional consideration. To make termination work in both directions (so the driver could be on the right end or the left end), you have to put a terminator at both ends.
VCC VCC | | > R1 R1 > > _ _ _ _ _ _ _ _ _ _ > __|\____|__| | |_____| | |_____| | |_____| | |_____| | |__|___/|__ |/ | L _|_ L _|_ L _|_ L _|_ L | \| driver > R2 C ___ C ___ C ___ C ___ R2 > driver IC > | | | | > IC | gnd gnd gnd gnd | gnd gnd
With two sets of resistors at each end, the DC power they consume from VCC is twice as much, as the DC drive current needed by the driver ICs has doubled. This is one reason the voltage divider approach as shown above is preferred. If R needs to be 100 ohms for example, and you had one 100-ohm resistor to VCC at each end, the driver needs to sink 100ma! But if you split R into two 200 ohm resistors, one to VCC and one to GND; and put that pair at each end as shown; now the driver only needs to sink or source 50ma. Only two of the four 200 ohm resistors are drawing current at any one time.
Since no one knows what cards people plug into the bus, or their capacitance, resistance, or inductance (wire length from edge connector to actual IC); trying to pick an [exact] R to properly terminate the buss is a lost cause. Another factor is the kind of "logic family" or devices used on those cards.
If the loads on each card edge connector are purely capacitive (like CMOS gates), the above analysis still works as long as you counted this extra capacitance as part of C when you figured out R. If the loads are TTL devices that draw a DC current, then their equivalent R's need to be figured into the value of R. When/if you can do this, you can still have a very clean bus waveform.
Worse yet; those capacitors and resistors don't really go to a perfect VCC or GND. The VCCs and GNDs on the cards's PC boards are themselves messed up and noisy from the long traces and various capacitive and resistive loadings. They are actually injecting noise into the bus!
Regarding "logic family" chips: the common chips for early S-100 were TTL and LSTTL. When you terminate them with a resistor pair (up to Vcc, down to ground), bus signal levels change from a high=5v and low=0.5v for unterminated; to high=3v and low=0.4v for terminated. But TTL has such wildly assymetric high/low levels (2v/0.8v) that you can degrade the high logic level without hurting overall noise immunity. Since TTL drivers can sink more [i.e. draw more current] than they can source, you often see resistor pairs like 220 ohms to VCC, and 330 ohms to GND. That particular paring provides a reasonable "high" logic level and a reasonable equivalent terminating resistance of 132 ohms.
Lee Hart later commented on how ham (amateur radio) designers dealt with the same problems of high frequencies and long runs of connections. - Herb
... hams are ever resourceful at getting things to work that you wouldn't think of.
Suppose you want to build a high-power solid state transmitter. That takes lots of MOSFETs in parallel. They are necessarily going to be spread out over a PC board and heatsink. That means long wires to connect them. At RF frequencies "long" is only a few inches -- so the delay produced by the wire lengths that parallel them cause them to be out of phase, and actually fight each other.
The standard technique is to mount the transistors in a circle, with the input gate drive and output coming from the center of concentric rings, so the wire length to every device is exactly the same. But that is awkward to build.
So, another approach is to put all the devices in a long line, like a computer bus. The gate drive signal hits the first device, then the next a few nanoseconds later, the next a few nanoseconds after that, etc.
To compensate for this propagation delay, the outputs are *also* taken from a long line, like a bus, which has exactly the same delay but in the reverse direction; the MOSFET gate closest to the input drive source has the *longest* bus line from its drain to the output. Thus, the pulses from each individual MOSFET recombine exactly in phase.
To make this work, you have to know *exactly* how much delay your bus produces, including the loading of the MOSFET's capacitance. So they start with theory (what board material, what trace width, what gate capacitance, etc.) and then "tinker" with it to actually make it work. They make boards the size of an S-100 motherboard work at 2 meters (144 MHz)!
Lee A. Hart
As I researched the various references to bus termination, I came across references to using Schottky diodes as terminators. If you put a pair of diodes in reverse bias order between the bus line and both ground and Vcc, then any voltages below ground or above Vcc are "shorted" accordingly. The energy (charge, voltage) is dissipated and so ringing is reduced. Schottky diodes have a lower forward voltage than ordinary diodes (or transistor PN junctions) and are also designed to turn on (or switch) faster, typically in a few nanoseconds. This kind of termination seems to have become poplular for faster busses and for memory arrays designed in the later 1980's when data speeds were in the hundreds of MHz.
Cypress Semiconductor has a number of Tech Notes on bus termination including the one cited by Lee Hart earlier in this discussion. That note suggests Schottky diodes will conduct at .3V to .45V, less than the .6V to .7V of ordinary diodes. I asked Lee Hart in private discussion about this option. He said:
"Schottky diodes are great when the problem is that the overshoot is so bad that it drives the bus voltage well below 0v and well over +5v, so the internal protection diodes in the chips conduct. [But] these are tiny crappy diodes, and can easily fail or cause problems like latch-ups. By clamping the voltage to +5.5v and -0.5v, the internal protection diodes won't conduct. But the schottkys won't do anything about the ringing, which can cause multiple clock edges."
In April 2004 Allison posted: "I have two N*S [NorthStar] systems, both have the same backplane, CPU and ram and when configured identically with FDC card to my non-surprize they don't behave the same. Reason, variations with in the same TTL family are enough to take marginally in to marginally out and resulting non function. One requires a simple 220/330 terminator to make it happy and even swapping the entire card set doesnt change which one required the termination, Likely due to IO at the end of the bus.
With that the best looking signals running a 10mhz N*S z80 card is with the cpu at the IO end and a 220/330 at the far end (near the front) with the ram and FDC around mid point. Moving the ram and IO around makes a difference too!. Reason is not all cards have the buffers close as possible to the edge connector and any long runs on the card(s) impact the backplane. I'd say the N*S is typical of 1980 design ruls and execution, not bad but if it were half as many slots it woul have been better.
Allison continued: I have two North*Star s100 crates, one is solid without termination, the other is identical save for one memory card.. good card too. The latter is flakey if the board are placed the same as the first. If the board is moved it's reliable or if a terminator (CCS board) is added it works in an unfussy way. Why? Difference in that one card's layout and how it impact the total bus. One could argue the N*S is a good or a poor S100 machine but it does reflect what S100 systems were in the ~1980 timeframe and as such was typical. By 1983-85ish everyone has started to figure out what was really needed to make S100 work (besides standards!)
My best backplane is a well laid-out and designed oddball 5 slot unit with 220/330 ohm termination at one end. No idea who made it. It's very clean. That one runs very nicely at any speed. The worst is a Wameco 22 slot unit that's very long, Rings badly even with the built in series termination 220 plus series cap to ground. Shorter is better.
FYI & OT: cooling some of the crates is as much a problem as the bus ringing. Many do not have airflow sufficient or balanced enough. The N*S is poorest near the FP. - Allison
Randy McLaughlin responded: "The worst system that I can remember working with was an Altair with two short S100 busses wired together (plus the front panel). The guy wanted to run a 4mhz Z80 and didn't like the suggestion of replacing the motherboard. - Randy
At hand I have the IEEE-696 specification for "S-100" bus lines, which says to terminate active driver or three-state driver lines with the equivalent of a minimum 180-ohm resistor per line to a common 2.7V source. Open collector lines should be terminated to a 360-ohm "pull up" to a 5V source. That is roughly consistent with other bus and TTL line termination schemes I saw in the 1970's and '80's. For instance, the original Intel Intellect MDS development system of 1975 uses a passive termination scheme on BCLK/ and CCLK/ lines (a 10MHz clock line driven by a 74S40 Schocky gate), of a 220-ohm resistor pull-up to +5, and a 330-ohm resistor pull-down to ground.
Several S-100 manufacturers offered bus termination cards or motherboards (bus boards) of all the kinds mentioned above. I'm looking at a 1980 description of Compupro's "Active Terminator", a short-height bus card. This card has a 2.7V source built from an op-amp with some transistor pairs to provide more current output from the op-amp. The 2.7V source feeds a 1K resistor to ground, and a common point to a string of individual 270-ohm resistors, each connected to a bus signal line (excluding power and ground lines). That common point is also connected to capacitors which provide filtering of low and high frequency noise and signals. The Compupro motherboard of 1980 has a similar scheme but uses SIP resistor packs with paralleled pairs of 560 ohms (or other values) at either end of each bus line; that schem provides equivalent terminating resistance but does it from both ends of the bus.
The California Computer Systems (CCS) 2520 extender/terminator card manual has a good explanation of passive, active, and "dynamic" bus termination methods. They call the use of capacitor-resistor networks "dynamic termination", but they suggest it is limited to slower speed uses of the S-100 bus - the 2MHz or slower cards of the early IMSAI/Altai- era. The CCS termination scheme is a 330-ohm resistor from the voltage source to each bus line; and optionally per lines a series resistor and capacitor to ground of 150 ohms and .01mF (a time constant of 7.5us). Their constant voltage source is a LM317T voltage regulator, a three-terminal voltage regulator in a TO-220 package. The regulation leg is connected between two 220-ohm resistors, one to ground and one to the output of the LM317T. The input of the '317 is to +8V, and the output is of course the constant voltage source feeding all the 330-ohm resistors. All three lines of the LM317T are bypassed with 4.7uF tantalum capacitors. (I'd recommend some .01uf bypass as well if I were building this.)
If anyone wants to point out other S-100 manufacturers of terminated busses, I'll reference them in this document if I have the docs for them. All my S-100 docs are referenced by manufacturer on my S-100 home page. Copies of any docs are available for a modest per-page service charge plus postage, contact me accordingly.
Theory of operation
The following is taken from the 1980 CCS manual. The design has a simpler voltage source than the Compupro but more comments about passive, active, and dynamic termination. My comments are in 's. - Herb
The inductance and capacitance of the S-100 bus wires of a system's motherboard can cause a number of problems, such as excessive ringing, overshoot and crosstalk. Such problems may occur in combination and may come and go with changes in system configuration. Terminating the bus alleviates these problems by placing a termination load on each line, causing induced voltages to be absorbed before the have the chance to degrade waveforms. Their major types of bus termination -- passive, active and dynamic -- are described below.
Passive termination returns a line to a fixed voltage developed by a resistive divider. Resistor values are generally chosen to establish a quiescent voltage above the logic's linear region (well above the lower voltage limit of a logical "1") and a termination resistance to ground compatible with the logic's internal impedance. Because the power supply is in effect an AC short between power and ground, the pairs of resistors appear to the lines in parallel; thus the resistor values should be twice the desired impedance. Using resistors in the range of 330 to 390 ohms provides an optimum TTL terminating match. However, because the S-100 bus has 94 lines that need to be terminated, this method places a continuous load in excess of .6 amps on the +5V DC power supply. For this reason the 2520 does not employ passive termination.
A more efficient scheme, active termination, develops the reference voltage with a regulator and returns the bus lines to the reference through isolating resistors. With 94 lines of the bus, the number of high and low [states] will in most cases be approximately equal, minimizing the average current requirement by allowing the nodes to cross feed (source and sink) to each other. Such a scheme is called active termination because the regulator actively supplies the reference current to stabilize the reference impedance. Primarily, active termination minimizes crosstalk by causing induced voltages to be absorbed more rapidly. Active termination can also slightly decrease response time my minimizing the worst-case transition distance from a floating level [of voltage] to a high or low logic level while maintaining the same slew rate. [The CCS design uses 330 ohm resistors for isolating resistors.]
Dynamic termination involves placing a resistor and capacitor in series between each bus line and ground. Values should be selected to minimize impedance and [RC] time constant. This kit is furnished with 150 ohm resistors and .01uF capacitors, which give a [signal] time constant of 7.5 microseconds. [This time constant is several times the R-C time constant of 150 X .01 = 1.5 microseconds.]
This method affects the rising and falling edges of bus signals and is used to eliminate overshoot and ringing. The speed of low-to-high and high-to-low transitions is degraded substantially enough, however, to make dynamic termination impractical for many high-speed (4Mhz) processors. This method is recommended primarily for 2MHz systems with strong bus drivers.
[The CCS voltage source is a LM317T three-terminal regulator, fed off the +8V line. There are two 220 ohm resistors in series across the output of the LM317T to ground. Their common point is connected to the regulation input of the 317. No specific voltage is specified for the output. All three regulator pins have 4.7uF tantalums to ground. I'd add some .01uF's as well.]
[In] choosing a configuration there are three possible choices: active termination, dynamic termination, or active-and-dynamic termination. In most cases active termination is preferable. Dynamic or active-and-dynamic terminations should be used only when active termination alone does not solve your bus problems.
The following is taken from the 1980 Compupro manual. This design has a more powerful voltage source than the CCS. My comments are in 's. - Herb
Active termination theory
The standard TTL termination is a 2.7V reference, comprising a 360 ohm and a 390 ohm resistor in series across the [5V] power supply; the TTL line terminates at the junction of these two resistors. This type of passive termination allows for proper sourcing and sinking of the TTL line, and keeps the impedance of the line to a minimum to minimize pickup of noise and crosstalk. Each one of these terminations, however, draws about 6.7mA from the power supply. So terminating 94 lines in this manner means a standby current draw of well over half an amp! These passive terminations don't just put a strain on your power supply; they waste energy and create heat inside your cabinet....
The active termination in the Compupro Motherboard take s advantage of the fact that there is an equivalent ACTIVE structure based around a voltage source and isolating resistor, that can accomplish the same results. Current can either source or sink through the 280 ohm resistance (two 560 ohm resistors in parallel) either dumping into or drawing from the voltage source. Terminating more lines simple means adding more 280 ohm resistors between the line and the voltage source. As a result the standby current is slashed to the standby current of the voltage source - about 15 or 20mA, which is quite a savings in energy.
...at any given moment, on 94 lines there will be a random mix of 1's and 0's. These tend to cancel out and thus reduce the current drive requirements of the voltage source. Nonetheless, ....the voltage source has enough capacity built-in to take care of the most adverse needs.
[The voltage source uses a 78L05 5V reference, which drives an op-amp via an adjustable resistive divider. The LM4250 op amp has two pairs of outboard transistors (Q1 2N3906 & Q2 2N3904; Q3 D44CX, Q4 D45CX TO-220's) to provide sufficient current on the voltage source line. That line drives the 94 270-ohm resistors to S-100 signal lines. Also across the voltage source line to ground are a 1K ohm resistor, and five 39uF tantalum capacitors. The terminator card version of this circuit is the same but has a cross the voltage source a 1K ohm resistor, two 39uF caps and three .01uf ceramic caps. - Herb]
[Note: Q3 and Q4 are likely similar to D44C8 and C45C8, 60 volt transistors. Data sheets for these parts are on the Web in 2011. - Herb]
[A later version of this design used 560-ohm SIP (single inline package) resistors: one set is at the BEGINNING of the bus, and one set at the END of the bus, so each line gets two resistors in parallel AND the bus is terminated at each end! But a 1983 version 12-slot Compupro bus card used 1.5K-ohm SIPs at each end. Thomas Fischer reported this resistance value earlier, he did not know why 1.5K ohm SIPs were used. - Herb]
In the fall of 2009, I worked on restoring an Ithaca Intersystems DPS-1 S-100 system. It's all Ithaca boards except Ithaca used a Morrow brand "Thinker Toys" Wunderbus model of motherboard. Here's
my notes about that motherboard and how I repaired it. The design is very similar to the Compupro motherboard.
STDbus is a 56-pin bus signal system on a 4 X 6 inch card intended for small "rack" or desktop
mounting. It was created by Pro-Log in
the mid-1970's, from their previous microprocessor cards which used various busses per processor. STDbus supports a variety of 8-bit, 16-bit, and later 32-bit processors. I call it out in this
document, as a matter of legacy bus standards.
The Pro-Log 7901A terminator board, consists of a collection of caps and SIP resistors, plus a reset circuit to a push button. The termination for each signal line is a series 100pF capacitor (101) from the STDbus pin, followed at the other end by a 100 ohm resistance to ground (101 SIP resistors). I actually measured and observed these values. The simple time constant is 100pf X 100 ohms = .010 microseconds. For time to switch between low and high logic voltages, the usual calculation is
the time from 10 to 90% of zero-to-Vcc volts: 2.2 X R X C. So that measure would be .022 microseconds, corresponding to 50MHz.
The Pro-Log 7106 motherboard, is described in the ProLog STDbus tech manual 1981. It describes
"passive AC termination" of 100 ohm grounded series resistor with a 470pF (.00047 uF) capacitor to signal lines. Again the time constant is 100 ohms X 470pf = .047 microseconds; and switching
time of 2.2 times that, or .1 microseconds, 10MHz.
- Herb Johnson, May 2023
This document copyright © 2023 Herb Johnson.
Legacy: Thinker Toys (Morrow) Wunderbus
Legacy: Pro-Log STDbus terminator
New Jersey, USA
To email @ me, see see my ordering Web page.
In the fall of 2009, I worked on restoring an Ithaca Intersystems DPS-1 S-100 system. It's all Ithaca boards except Ithaca used a Morrow brand "Thinker Toys" Wunderbus model of motherboard. Here's my notes about that motherboard and how I repaired it. The design is very similar to the Compupro motherboard.
STDbus is a 56-pin bus signal system on a 4 X 6 inch card intended for small "rack" or desktop mounting. It was created by Pro-Log in the mid-1970's, from their previous microprocessor cards which used various busses per processor. STDbus supports a variety of 8-bit, 16-bit, and later 32-bit processors. I call it out in this document, as a matter of legacy bus standards.
The Pro-Log 7901A terminator board, consists of a collection of caps and SIP resistors, plus a reset circuit to a push button. The termination for each signal line is a series 100pF capacitor (101) from the STDbus pin, followed at the other end by a 100 ohm resistance to ground (101 SIP resistors). I actually measured and observed these values. The simple time constant is 100pf X 100 ohms = .010 microseconds. For time to switch between low and high logic voltages, the usual calculation is the time from 10 to 90% of zero-to-Vcc volts: 2.2 X R X C. So that measure would be .022 microseconds, corresponding to 50MHz.
The Pro-Log 7106 motherboard, is described in the ProLog STDbus tech manual 1981. It describes "passive AC termination" of 100 ohm grounded series resistor with a 470pF (.00047 uF) capacitor to signal lines. Again the time constant is 100 ohms X 470pf = .047 microseconds; and switching time of 2.2 times that, or .1 microseconds, 10MHz.
- Herb Johnson, May 2023
This document copyright © 2023 Herb Johnson.