Peter Hill described the  bipolar PROM addressing chips on the
Zilog ZDS system, as he tries to modify or restore these chips in 2010.
Here's his notes. - Herb Johnson, July 2010

[The address selectors on the Zilog ZDS systems are] 7603 Bipolar
tri-state 32x8bit PROMs.

I changed memory map to try to put the CPU card memory at 0000H
and expansion memory at 4000H and now nothing works as I seem to have
a memory addressing conflict. In addition to the PROM there are 3 DIL
headers that have solder links. I tried to reverse the changes but
failed some years ago.

Contents of PROM (for 48K - 3x16K roms, card can have 12K - 3x4K roms
fitted but then only decodes 11, 12, 13). It actually only uses 4 bits
for output - D4 refresh, D5 cas1, D6 cas2, D7 cas3.

standard for RIO
addr output
00 1F
01 1F
02 1F
03 1F
04 1F
05 1F
06 1F
07 1F
08 1F
09 1F
0A 1F
0B 1F
0C 1F
0D 1F
0E 1F
0F 1F
10 FF
11 CF
12 CF
13 CF
14 FF
15 FF
16 FF
17 FF
18 CF
19 AF
1A AF
1B AF
1C AF
1D 6F
1E 6F
1F 6F

for CP/M (and RIO), needs some mods to CPU card to enable page 0
ROM/RAM switch.
addr output
00 1F
01 1F
02 1F
03 1F
04 1F
05 1F
06 1F
07 1F
08 1F
09 1F
0A 1F
0B 1F
0C 1F
0D 1F
0E 1F
0F 1F
10 6F
11 CF
12 CF
13 CF
14 FF
15 FF
16 FF
17 FF
18 CF
19 AF
1A AF
1B AF
1C AF
1D 6F
1E 6F
1F 6F

FOr the TTL decoder I made, it was easier to decode the 3 16K ram
banks at 0000H, 8000H and C000H (CPU card at 4000H).
00 1F
01 1F
02 1F
03 1F
04 1F
05 1F
06 1F
07 1F
08 1F
09 1F
0A 1F
0B 1F
0C 1F
0D 1F
0E 1F
0F 1F
10 6F
11 6F
12 6F
13 6F
14 FF
15 FF
16 FF
17 FF
18 AF
19 AF
1A AF
1B AF
1C CF
1D CF
1E CF
1F CF
--
Peter D Hill