Ithaca Intersystems DPS-1
jumpers as set in the Robinson system as tested Feb 2016
last updated Mar 6 2016 HRJ

CPU Z80 II no rev, no ROM on board

J1  open
JA1 B-C  was standard ROM (stnd ROM) 2708 at F000H, should be A-B for 2708
JA2 B-C  was stnd ROM, for 2708 shold be A-B
JB1 B-C  A15 = 0
JB2 B-C  A14 = 0
JB3 B-C  A13 = 0
JB4 B-C  A12 = 0
JB5 B-C  stnd ROM A11 = 0
JB6 B-C  stnd ROM A10 = 0
JC1 A-B  $ std. addr trans don't care
JC2 B-C  $ std. addr trans don't care
JC3 A-B  $ std. addr trans don't care
JC4 B-C   mem mgmt dont care,  
JC5 B-C   mem mgmt dont care
JC6 A-B   mem mgmt translator disabled
JD1 A-B  JD1-6 standard E0 I/O address   
JD2 A-B    
JD3 A-B  
JD4 B-C  
JD5 B-C  
JD6 B-C  
JE1 A   stnd ROM 
JE2 A   stnd ROM
JF  B-C  $ local intr contrller accept
JG  A-B  $ 4MHz
JH1 A-B  $ partial latch
JH2 A-B  $ M1 1 wait
JH3 B-C  $ mem no wait
JH4 B-C  $ I/O no wait
JH5 B-C  $ EPROM 0 wait <--A-B 1 wait is suggested
JI  B-C  $ local intr controller assert
JJ1 B-C  $ no EPROM, no jmp
JJ2 A-B  $ VI enab
JJ3 B-C    bus strobes enabled with front panel <-- should be A-B w/o front panel!!
JJ4 A-B
JK  B-C - jump to off board memory
JL  A-B
JM  A-B 
JN  A-B  NMI to NMI
JO  A-B  MWRT enabled, no front panel

Floppy   FDC 2 IA 2020 rev A

appears to be as standard setup per page 19 of hardware manual
ex J16, J20. 2708 PROM on board. 8" dlroppy drive 

J1  1A-B, 2A-B
J2  B-C (prom 1 wait)
J3  1-15,4-14,5-12,8-11 (2 X 9 pin header, see manual for numbering)
J4A A-B
J4B A-B
J4C B-C
J4D A-B
J5  A-B
J6  B-C
J7  B-C
J8  B-C
J9  B-C
J10 A-B
J11 A-B
J12 A-B
J13 B-C  
J14 A-B
J15 all B-C ( extended addr 00H)
J16 A7-B7 (VI1 connected to bus)
J17 row 2-3
J18 row 1-2
J19 all B-C
J20 A-B (24 bit addr)
J21 All B-C (EPROM addr = 0000H)

memory    IA-2030 64K Rev A
pay attention to jumper designations in manual
type 6 - Z80II CPU, IEEE mode, 4116, 64K, 8/16 bit

J1 open 
J2 center pin wired to J4C???
J3 no jumpers , PC board has trace from A-B
J4 no jumpers, PC board has trace from A-B
J5 A-B  
J6 A-B  
J7 B-C
J8 jumper C
J9 jumper D
J10 top = A, J10 bottom = C
J11 B-C
J12 top = A (PC board trace), J12 bottom = D
J13 top = A,  next = C,   next = G (trace),  bottom = I(trace)
J14 B-C
J15 B-C
J16 open
SW1 all switches closed (All banks enabled)
J17 B 
J18 A
J19 B (24-bit address)
J20 A
SW2 all switches closed (unused as J19 = A)

Serial I/O VIO  IA-1190 rev B 

J1 - header as passive current loop 
J2 - header as active current loop 
J3-0 B-C (non inverted)
J3-1 B-C
J3-2 B-C
J3-3 B-C
J3-4 B-C
J3-5 B-C
J3-6 B-C
J3-7 B-C 
J4, J5 are parallel port  
J4-1 open  
J4-2 A-B
J4-3 A-B
J4-4 B-C
J4-5 open  
J4-6 A-B
J5-1 open  
J5-2 A-B
J5-3 A-B
J5-4 A-B
J5-5 open  
J5-6 B-C
SW1 - all closed, lines on parallel port see manual
J6 set as independent interrupts
J61 B-C
J62 B-C
J63 B-C read man
J64 A-B read man
J7  V7A to center (V7 line to A controller)
    V2B to center (V2 line to B controller)
J8A is RS  (port A RS-232)
J8B is RS  (port B RS-232)
J9  F to 6 IRQ5
    H to 7 IRQ6
    I to 8 IRQ7
J10 + to center post, software interr response read        
    W to 1   (1 wait states)
J11 7 to -, 6 to - 5 to -, (address 00H, I/O mapped 8-bit)
    M to -, X to -
J12 all open
J13 A-B (between U20 and U21), independent interrupts