Ithaca Intersystems DPS-1 jumper settings 
as taken from BIOS manual for BIOS 4c and from 64K hardware manual
comments added HRJ Mar 10 2016

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Standard BIOS 4c User's Manual Page 30,31

Appendix A

Jumper Configurations For Intersystems Series II Boards

These are the jumper configurations required to run the
Intersystems standard BIOS. Depending upon your particular
application, some jumpers may be different. This list s
intended only as a <quick reference guide; for details on the
significance of each jumper, consult the manuals for the
individual boards.

MPU-80:

J1  open
JA1 B-C  
JA2 B-C   
JB1 A-B  A15 = 1 address F000H
JB2 A-B  A14 = 1
JB3 A-B  A13 = 1
JB4 A-B  A12 = 1
JB5 B-C  stnd ROM A11 = 0
JB6 B-C  stnd ROM A10 = 0
JC1 A-B    std. addr trans  
JC2 B-C    std. addr trans  
JC3 A-B    std. addr trans  
JC4 B-C  mem mgmt 
JC5 B-C  mem mgmt  
JC6 A-B   mem mgmt translator dsbled
JD1 A-B  JD1-6 standard E0 I/O address   
JD2 A-B    
JD3 A-B  
JD4 B-C  
JD5 B-C  
JD6 B-C  
JE1 A   stnd ROM 
JE2 A   stnd ROM
JF  B-C  $ local intr contrller accept
JG  A-B  $ 4MHz
JH1 A-B  $ partial latch
JH2 A-B  $ M1 1 wait
JH3 B-C  $ mem no wait
JH4 B-C  $ I/O no wait
JH5 A-B  $ EPROM 1 wait  
JI  B-C  $ local intr controller assert
JJ1 B-C  $ no EPROM, no jmp
JJ2 A-B  $ VI enab
JJ3 B-C    bus strobes enabled with front panel <-- should be A-B w/o front panel!!
JJ4 A-B
JK  A-B  
JL  A-B
JM  A-B 
JN  A-B  NMI to NMI
JO  A-B  MWRT enabled, no front panel or B-C with front panel
 FDC 2 IA 2020, 8" floppy drives

J1: 1 is A-B, 2 is A-B
J2: B-C PROM 1 wait
J3: 8" floppy drive compensation
     pin 1 connected to pin 15
     pin 4 connected to pin 14
     pin 5 connected to pin 12
     pin 8 connected to pin 11   look for header pinout in manual
J41 A-B
J42 A-B
J43 B-C
J44 A-B
J5 A-B
J6 B-C
J7 B-C
J8 B-C
J9 B-C
J10: A-B
J11: A-B
J12: A-B
J13: B-C
J14: A-B
J15: all rows B-C (extended addr 00H)
J16: shunt the third pair of pins from the bottom (VI1 to bus)
J17: B-C
J18: A-B
J19: all rows are B-C
J20: A-B 24-bit addr
J21: all rows are B-C, EPROM address 0000H

VIO-O and VIO-1:

CLA header (at J1) is 1-2, 3-4, S-6, 9-10, 11-12, 13-14.
The header is supplied connected as described.

CLB header (at J2) is 1-2, 3-4, 5-6, 9-10, 11-12, 13-14.
The header is supplied connected as described.

J3 (VIO-1 only): all rows are B-C
J4, J5 specific to parallel ports
J4: 1 is open, 2 is B-C, 3 is A-B, 4 is B-C, 5 is open, 6 is A-B
J5: 1 is open, 2 is B-C, 3 is A-B, 4 is B-C, 5 is open, 6 is A-B
J6 set as independent interrupts
J6 (VIO-1 only): 1 is B-C, 2 is B-C, 3 is B-C, 4 is A-B
J7 (VIO-1 only): 2 is center to B; all others are open.
J8: both are center to RS.
J9 (VIO-1 only): shunt F-6.
J10: center to + and 1 to w (soft inter response, 1 wait state)
J11: all center to -  (address 00H, I/O mapped 8-bit)
J12: not used.
J13 (VIO-1 only): A-B. (independent interrupts)
DIP switch SW1: all switches open, for parallel ports

6SIO:

Header H1 is 1-2, 3-4, 5-6, 9-10, 11-12, 13-14.
Header H2 is 1-2, 3-4, 5-6, 9-10, 11-12, 13-14.
Both headers are supplied connected as described.
Header H3 is 3 to 15, 14 to 38, 13 to 39.
J1: All are A-B.
J2: A-B.
J3: A-B.
J4: shunt A-B third pair of pins from the top.
J5: shunt A-B sixth pair of pins from the top.
J6: B-C.
J7: A-B.
J8: B-C.
DIP switches SW1 and SW2 are all closed.

Following NOT from 4c BIOS manual, but from 64K manual Rev 0

memory    IA-2030 64K Rev A
pay attention to jumper designations in manual
type 6 - Z80II CPU, IEEE mode, 4116, 64K, 8/16 bit

J1 open 
J2 center pin wired to J4C 
J3 no jumpers , PC board has trace from A-B
J4 no jumpers, PC board has trace from A-B
J5 A-B  
J6 A-B  
J7 B-C
J8 jumper C
J9 jumper D
J10 top = A, J10 bottom = C
J11 B-C
J12 top = A (PC board trace), J12 bottom = D
J13 top = A,  next = C,   next = G (trace),  bottom = I(trace)
J14 B-C
J15 B-C
J16 open
SW1 all switches closed (All banks enabled)
J17 B 
J18 A
J19 B (24-bit address)
J20 A
SW2 select a bank address A16-A23 as per manual

memory setting type 5 - Z80II CPU, extended addr, 4116, 64K, 8 bit

J1 open 
J2 B-C
J3 no jumpers , PC board has trace from A-B
J4 no jumpers, PC board has trace from A-B
J5 B-C  
J6 A-B  
J7 B-C
J8 jumper C
J9 jumper D
J10 top = B, J10 bottom = C
J11 A-B
J12 top = A (PC board trace), J12 bottom = C
J13 top = B,  next = E,   next = G (trace),  bottom = I(trace)
J14 A-B
J15 A-B
J16 open
SW1 all switches closed (All banks enabled)
J17 C 
J18 A
J19 B (24-bit address)
J20 B
SW2 select a bank address A16-A23 as per manual