Operator's Console, from the DEC "PDP 11/20 Handbook", 1969
copy at http://research.microsoft.com/%7Egbell/Digital/DECMuseum.htm


The PDP-11 Operatorís Console has been configured to achieve convenient control of the system. Through switches and keys on the console, programs or information can be manually inserted or modified. Also.indicator lamps on the console face display the status of the machine, the contents of the Bus Address Register and the data at the output of the data paths. The console is shown in Figure 12-1.

[PDP 11/20]


The console has the following indicators and switches:

INDICATOR LIGHTS-The indicators signify specific machine functions, operations, or states. Each is defined below.

1. Fetch - indicates that thdcentral processor is in the state of fetching an instruction.
2. Execute - indicates that the central processor is in the state of executing an instruction.
3. Bus - indicates that a peripheral is controlling the bus. It is lit when BBSY (Bus Busy) is asserted, unless the processor (which includes the Console) is asserting BBSY.
4. Run - indicates that the processor is running. It monitors the control flip-flop for the internal clock.
5. Source -indicates that the central processor is. obtaining source data except from an internal register.
6. Destination - indicates that the central processor is obtaining destination data (except from an internal register).
7. Address -identifies the source or destination address cycle of the central processor, using two lights that are decoded zero, one, two, or three.

When references are made via the Unibus to the addresses, the lights tell the machineís source or destination cycle. For an internal register reference, there is a "zeroth" addressing operation.

REGISTER DISPLAYS-The Operatorís Console has an 18-bit Address Register Display and a 16-bit Data Register Display. The Address Register Display is tied directly to the output of an l&bit flip-flop register called the Bus Address Register. This register displays the address of data examined or deposited.

The 16-bit data register is divided on the face of the console by a line into two 8-bit bytes. This register is tied to t,he output of the processor data paths and will reflect the output of the processor adder.

SWITCH REGISTER-The PDP-11/10 and PDP-11/20 can reference 2**16 bytes addresses. However, the Unibus has expansion capability for 2**18 byte addresses. In order that the console can access the entire 18-bit address scheme, the switch register is 18 bits wide. These bits are assigned as 0 through 17. The highest two are used only as addresses. A switch in the "up" position is considered to have a "1" value and in the "down" position to have a "0" value. The condition of the 18 switches can be loaded into the bus address register or any memory location by using the appropriate control switches which are described below.


The switches listed in item 5 of the "Console Elements" have these specific control functions:

1. LOAD ADDR - transfers the contents of the 16-bit switch register into the bus address register.

2. EXAM - displays the contents of the location specified by the bus address register.

3. DEP - deposits the contents of the low 16 bits of the switch register into the address then displayed in the address register. (This switch is actuated by raising it.)

4. ENABLE/HALT- allows or prevents running of programs. For a program to run, theswitch must be in the ENABLE position (up). Placing the switch in the HALT position (down) will halt the system.

5. START - starts executing a program when the ENABLE/HALT switch is in the ENABLE position. When the START switch is depressed, it asserts a system initialization signal; the system actually starts when the switch is released. The processor will start executing at the address which was last loaded by the LOAD ADDR key.

6. CONT - allows the machine to continue without initialization from whateyer state it was in when halted.

7. S/INST-S/CYCLE - determines whether a single instruction or a single bus cycle is performed when the CONT switch is depressed while the machine is in the halt mode.

When the system is running a program, the LOAD ADDR, EXAM, and DEPOSIT functions are disabled to prevent disrupting the program. When the machine is to be halted, the ENABLE/HALT switch is thrown to the halt position. The machine will halt either at the end of the current instruction, or at the end of the current bus cycle, depending upon the position of the S/INST-S/CYCLE switch.


When the PDP-11 has been halted, it is possible to examine and update bus locations. To examine a specific location, the operator sets the switches of the switch register to correspond to the locationís address. The operator then presses LOAD ADDR, which will transfer the contents of the switch register into the bus address register. The location of the address to be examined is then displayed in the address register display. The operator then depresses EXAM. The data in that location will appear in the data register display.

If the operator then depresses EXAM again, the, bus address register will be incremented by 2 to the next word address and the new location will be examined. In the PDP-11, the bus address register will always be pointing to the data currently displayed in the data register,.The incrementation occurs when the EXAM switch is depressed, and then the location is examined.

The examine function has been designed so that if LOAD ADDR and then EXAM are depressed, the address register will not be incremented. In this case, the location reflected in the address register display is examined directly. However, on the second (and successive) depressings of EXAM, the bus address register is incremented. This will continue for successive depressings as long as another control switch is not depressed.

If the operator finds an incorrect entry in the data register, he can enter new data there by putting it in the switch register and raising the DEP key. The address register will not increment when this data is deposited. Therefore. when the operator presses the EXAM key, he can examine the data he just deposited. However, when he presses EXAM again, the system will increment.

If the operator attempts to examine data from, or deposit data into, a non-existent memory location, the "time out" feature will cause an error flag. The data register will then reflect location 4, the trap location, for references to nonexistent locations. To verify this condition, the operator should try to deposit some number other than four in that location; if four is still indi- cated, this would indicate that either nothing is assigned to that location, or that whatever is assigned to that location is not working properly.

When doing consecutive examines or consecutive deposits, the address will increment by 2, to successive word locations. However, if the programmer is examining the fast registers (the "scratch pad" memory), the system only increments by 1. The reason for this is that once the switch register is set properly, the programmer can then use the four least significant bitsof the switch register in examining fast memory registers from the front panel.

To start a PDP-11 program, the programmer loads the starting address of the program in the switch register, depresses LOAD ADDR, and after ensuring that the ENABLE/HALT switch is in the ENABLE position, depresses START. The program will ,start to run as soon as the START switch is released.

The Run indicator lamp is driven off the flip-flop that controls the clock. Normally, when the system is running, not only will this light be on, but the other lights (Fetch, Execute, Source, Destination, the.Address lights, and the Address and Data registers) will be flickering. If the run light is on, and none ofthe other indicators are flickering, the system could be executing a "wait" instruction which waits for an interrupt.

While in the halt mode, if the operator wishes to do a single instruction, he places the S/INST-S/CYCLE switch in the S/lNST position and depresses CONT. When CONT is depressed, the console momentarily passes control to the processor, allowing the machine to execute one instruction before regaining control. Each time the CONT switch is depressed, the machine will execute one instruction.

Similarly, if the operator wishes to have the machine perform a single bus cycle, he places the S/INST-S/CYCLE switch in the S/CYCLE position and presses CONT. The machine will then perform one complete bus cycle and halt. The operator cannot do an examine or deposit function at the end of a single bus cycle unless the cycle ends coincidental with the end of an instruction. This prevents altering machine flow. Only when the machine is at the end of an instruction and in the halt modeícan the examine or deposit functions operate.

To start the machine running its program again, the operator places the ENABLE/HALT switch in the ENABLE position, and depresses the CONT switch.