Tech Note: Reduced power operation, March 29 2010 by Lee Hart [Refer to the 1802 Membership card schematic for details. Additional information added in []'s by Herb Johnson.] Power connector --------------- The power connector at P4 has +power on pin 1, ground on pin 4, and a jumper between 2 and 3. To "power off", set the CLEAR switch low to stop the CPU, then unplug the power connector at P4. This automatically disables the LEDs (the biggest power user). [The LED resistors are grounded through the jumper between 2 and 3.] Low Power ROM/RAM ------------------ The original plan was to use true CMOS RAMs, where simply switching to LOAD or CLEAR or stopping the clock (by unplugging the front panel board, for example) was all it took. But these RAMS seem to have become unobtainium. [Modern RAMs and ROMs consume much more power, and more still when selected via CS, etc.] Early CMOS ROM and RAM chips: RCA RAMs were MW or CDM 6116 or 6264. Harris or Intersil HM65xxx numbers are the RAMs, HM66xxx numbers are the ROM/PROM/EPROMs. Or, Toshiba TC55xx. The xx numbers are like the other CMOS chips; 6516=2k bytes, 6564=8k bytes 65256=32k, etc. [More modern CMOS ROMs or RAMs usually have a "C" in their name, and often have a "-L" suffix. Check their data sheets to find the lowest power version of their product line. For instance, the SEC brand KM62256CLP-7L, from the 1990's but still in production. 20uA standby, the lowest in that design series, most are 100uA. But the RCA early CMOS chips consumed 1uA in standby! - Herb] Micropower applications ----------------------- For micropower operation, I planned to use the Membership CPU board by itself, without the front panel. In this case, "+power" is pin 13, "common" is pin 1 or 30, and your on/off switch connects pins 13 to 14. Parts R4 R6 R7 C2 C3 are designed to minimize power when the front panel board is unplugged. When you turn off the power switch, R4 and R6 pull RUN (J1 pin 14) low. C2 discharges through R4. In about 47 msec, /CLEAR goes low and stops the CPU. Meanwhile C3 discharges through R7. In about 100 msec, it pulls pin 12 of U4D low and stops the clock. When you turn power back on (short J1 pins 13-13), D10 recharges C3 immediately, starting the clock. /CLEAR is still held low by C2, providing the power-on-reset. R6 charges C2. In about 10 msec, /CLEAR goes high and the CPU begins execution. Standby mode for ROM/RAM ------------------------ I worked on the Membership board some this weekend. I figured out a circuit that adds a transistor to control chip select for the RAM/EPROM. [Deselected RAM and ROM consume much less power.] old: A15 to U2 /CE new: A15 to source of Q1 (2N7000 n-channel MOSFET) TPB to gate of Q1 /CE to drain of Q1 /DMA-OUT was tied directly to VCC, instead of through a pullup resistor in R5. This freed a resistor, which pulls /CE high when Q1 is off. Operation: U2 /CE is low when TPB is high and A15 is low. TPB is high for 1/8th of the time (1 out of 8 clock cycles during each CPU bus cycle. So the effect of this is to cut memory chip power consumption by 8:1. TPB is also low when the CPU is in RESET, keeping the memory off when not running. -- Lee Hart