http://www.retrotechnology.com/memship/reset_jump.txt "Jump-on-Run" circuit and descriptions by Lee Hart For 1802 Membership Card Rev L CPU via front-panel. Written or quoted from Lee Hart prior to Mar 2022 last updates Herb Johnson Mar 9 7PM, made available to Lee Hart for corrections this version for preliminary publication Herb Johnson Apr 4 2022 How-to-operate instructions added June 16 2023, from Lee Hart How to operate the jump-on-run circuit by Lee Hart -------------------------------------- In June 2023, Lee Hart explained the run-on-jump operation this way: "To use the power-on-jump to 8000h feature of the Membership Card rev.L, start with the WAIT and CLEAR switches both up (the RUN position), and with the read/write switch in the RAM position. 1. Flip the CLEAR switch down. (Leave the WAIT switch up). 2. Hold down the IN button,and at the same time 3. flip the CLEAR switch up (RUN position). 4. Release the IN button." - Lee Hart "Jump-on-Run" circuit by Lee Hart --------------------------------- PNP || C6 [see notes for value] Q1 FJN4303 -----+---||---RUN/CLEAR switch | | || V | 22K B |/ E > R9 /IN button----/\/\----| > 3.3K |\ C | U3 Addr latch | GND U4 Addr decoder ------ R8 | ------- A15 |>----/\/\-------+--------->| A | 3.3K | B ============================================== Overview of essential actions, When /IN is held and RUN/CLEAR switch is flipped to RUN: ------------------------------------------------------ 1) 1802 goes from RESET to RUN in 9 clock cycles; at 4MHz, .25 uSec/clock, that's 2.25 uSec; at 1.8MHz, .556 uSec/clock that's 5.0 uSec. Then the 1802 executes instructions at whatever clock cycles they each take. Each bus cycle takes 8 (not 9) clock cycles. at 4Mhz, .25 X 8 = 2.0 uSec at 1.8Mhz, .556 X 8 = 4.45 uSec 2) At the same time, A15 is forced high by cap and transistor until cap (dis)charges through 3.3K resistor from about 5V, to where the voltage no-longer forces A15 "high". That time period depends on the capacitor value, not clock rates. 3)So the ROM as jumpered to 8000H, is from RESET to RUN for that period, will be addressed by the 1802 as if it's at 1802 address 0000H. 4) A program at the beginning of ROM, must set the 1802 program-counter to addresses at 8000H where the ROM normally resides, to run after normal A15 addressing is restored. The program should also disable interrupts if interrupts are part of the rest of the program. Almost the simplest program would be: 71 00 DISable interrupts C0 80 00 JuMP to 8000H This takes 5 bus cycles (40 clocks) at 4 MHz, 2.0 X 5 = 10uSec at 1.8Mhz, 4.45 X 5 = 22.3uSec 5) So the RC delay has to be at least that long, plus the 1802 reset time. at 4Mhz, that's 2.25uSec from reset to run + 10uSec program = 12.25uSec at 1.8MHz that's 5uSec from reset to run + 22.3uSec program = 27.3uSec ==================================================== State descriptions by Lee Hart some edits by Herb Johnson ---------------------------- Start with the IN button up (/IN=5v), Run/Clear switch down (CLEAR=0) - 1802 is sitting idle in CLEAR mode - Q1 emitter=0v (pulled down by 3.3k) - Capacitor has 0v across it (since both ends are 0v) - Q1 base=5v (pulled high by 22k from /IN) - Q1 collector open (since base-emitter junction is reverse-biased) - so A15 from 1802 passes unhindered to address decoder IN button (/EF4) is not pressed, base high; RUN toggled high (CLEAR=1) - normal 1802 RUN mode operation; it starts execution at 0000h - right end of capacitor goes to 5v (because RUN=5v) - left end of capacitor momentarily spikes up to 5v, but the 3.3k *charges* the left end down to 0v - but Q1 stays off, because both base and emitter are at 5v - so Q1 collector is open - so A15 from 1802 passes unhindered to address decoder - 1802 executes from 0000H as it finds instructions IN button not pressed, Flip switch to CLEAR (CLEAR=0) - 1802 in reset <--- - left end of capacitor momentarily spikes to -5v This does not turn the transistor on, because it only reverse-biases the base-emitter junction - *capacitor discharges at the left end from -5V to 0V * through 3.3K *cap charges from /IN, 22K, thru b-e junction to almost 5V* - Q1 is still open/off, can't pull decoder line so no effect on A15 press and hold IN button (sets /EF4 low), CLEAR still 0V - 1802 still in reset - emitter at 5V by cap, base at 0V, so transistor is ON - address line pulled up by collector, forces A15 high - A15 high until capacitor left end is *discharged* to 0v by base current (22k) and 3.3K current and collector current - once Q1 emitter returns low, Q1 must turn OFF, no matter if /IN is 0v or 5v holding IN button, flip switch from CLEAR to RUN (with run/wait already in RUN position) - 1802 from RESET to RUN state in *9* clock cycles - capacitor right end goes to 5v (CLEAR=high) - so capacitor left end momentarily goes to 5v - Q1 base=0v, so Q is forward-biased and transistor turns ON - transistor ON, holds A15 high - as cap charged on left to 0V by 3.3K. - then transistor turns off, and A15 operates as driven - so during cap charging-time, A15 is forced high until charged release IN button, RUN still active (CLEAR=high) - 1802 still in RUN state - /IN high, pulls base high thru 22K; emitter low so transistor OFF - reverse bias on b-e junction, capacitor stays charged to 0V on left - transistor still inactive, so A15 operates as driven =================================================================== What capacitor & resistor values determine how much delay? ------------------------------------------------------- Lee Hart, Mar 8 4:47PM: "Some measured values and timings are as follows (actual circuit): C6=0.022uF, R8=3.3k, R9=3.3k = 20us C6=0.047uF, R8=3.3k, R9=3.3k = 40us C6=0.1uF, R8=3.3k, R9=3.3k = 80us <-- this is what I plan to use" "0.01uF would have yielded 10us, which is too short to work." "I also experimented with R9=10k and R9=100k. They produced longer delays per uF, but the resting voltage across R9 was higher. When the IN button is up, the transistor has two 22k resistors in series between base and emitter. These form a voltage divider with R9, so it doesn't fully discharge C6. With R9=3.3k, there is only 0.35v across it when IN button is up; that's close enough to 0v to get the proper effect when the circuit becomes active." - Lee Hart Other notes from Lee Hart: -------------------------- 1) Some ROM programs take more instructions to set the PC to 8xxx. For example, the RCA VIP takes 6 instructions, and at 1.8MHz that takes 57 uSec for initialization and those 6 instructions. Adding 39.6uSec from reset, this circuit at that clock rate would need to take 100uSec to be safe. For Chuck's MCSMP20J monitor at 4MHz, this circuit needs to delay about 20uSec. So it looks like I need to lengthen it to about 100 usec to be safe. 2) The RC values of 3.3K and 0.01uF gave me a 30 uSec pulse in theory; but it's 20 uSec by actual measurement. It's because I just used R x C as the time constant. But that's the time to reach 37% {of final voltage], while an actual CMOS input has a [logic switching voltage] threshold of 50%. The pulse decays to 50% sooner, so the pulse is shorter. 3) I don't think this circuit is practical with LSTTL. The input threshold [for those inputs are] variable, and the input current [would be higher and so] require much lower value resistors, and proportionately higher values of capacitance. If [LSTTL is tried, it will have] the kind of problems we saw in the "bad old days" with RC networks and one-shots in S-100 cards.