The following information was copied from either Web page linked below. https://www.macgurus.com/forums/archive/index.php/t-17827.html https://www.macgurus.com/forums/showthread.php?17827-WTH-is-a-bank It's an archive or the thread, on a forum, on macgurus.com: MacGurus Technical Forums > General Hardware and Software Discussions > Memory and CPU Discussions > subject: WTH is a "bank?" The thread started in 2001. "trag" who is/was a "Guru Moderator", responded on date 12-08-2010, 12:15 PM, as follows. ---------------------------- Nine years late, but I probably didn't understand the material as well nine years ago... Terms to consider, SIMM, DIMM, Single Sided, Double Sided, Banks or Banked. The distinction between SIMM and DIMM is found on the memory module (SIMM or DIMM) connector -- the pins down along the bottom edge of the memory module. A SIMM has a single row of pins. "But wait, I see pins on both side, isn't that double?" Yes, but electrically, it's one row of pins. Each pin is electrically connected to the pin opposite it on the flip side of the module. On most SIMMs, if you look closely, you'll see a tiny copper lined hole right at the top of each pin connecting it to the pin on the opposite side of the SIMM. When you look into a SIMM socket, you'll see that the contacts for both sides of a module are made out of a single piece of wire bent to touch the pin on both sides of the board. A DIMM has two rows of pins. The pins on each side of the module are electrically distinct. So, if the module is 84 pins long, it actually has 168 distinct pins, eight-four on each side. Frankly, I'm not sure what the import of single and double sided is, other than to confuse people. I think folks try to use it as a short hand for banks. However, you can have a single banked module with chips on both sides or a double banked SIMM with chips only on one side depending on how the circuit board is laid out. As one might imagine, it's all about the electrical connections. Okay, now on to the complicated stuff. To understand banks you'll need to understand something about how memory is addressed. In this case, I'll only be discussing FPM/EDO and possibly SDRAM (haven't looked at SDRAM specs.) DDR RAM does the same things as what I'm going to describe, but some of the details are so different as to make it a distinct topic. The first thing to understand about memory is addressing. This is essential to understanding banks. I'm sorry, but there's no avoiding it. Addressing is how the computer keeps track of where it has put your data in the memory. The addresses are just numbers and they start at 0 and go up to some number which is related to the module's capacity. On early 30 pin SIMMs there were 12 possible address lines or wires. Each address line can represent a 1 or a 0, they are an electrical representation of a binary number. So if we have twelve digits, and we're using base 2 (binary), how high can we count? 4096. Not very high. So how do you get a 16MB SIMM with only 12 address lines? Simple, the computer sends a 12 bit (binary digits) address. Then the computer sends another 12 bit binary address. The memory gathers them up, strings them together and makes a 24 bit number out of them. This is called address multiplexing. A 24 bit number provides 2^24 or ~16M addresses. 30 pin SIMMs are one byte wide, so 16M addresses yields 16MB of capacity per SIMM. What is width? When the computer gives the RAM an address, there is more than 1 bit of data stored at that address. How many bits? That's the data width. A 30 pin SIMM is 8 bits wide or one byte wide (eight bits to a byte). If your computer (such as the Mac II family) uses four 30 pin SIMMs at a time, then it is putting them together to get more width, in this case 4 X 8 = 32 bits of data width. So a 30 bit SIMM has 12 address lines and is 8 bits wide. From this we deduce that the maximum capacity is 2^(12 X 2) X 8 = 16MB. The (12 X 2) is simply 12 address bits times 2 because of the multiplexing. Then we figure the total number of addresses from the number of address bits using the 2^. And X8 takes care of the eight bit width. There's one more thing we need to know about 30 pin SIMMs before we can move on to the fun part. If you've been following closely, then a few paragraphs back you were probably asking yourself, "But how does the memory tell the difference between when it's getting the first 12 address bits and the last 12 address bits? Why doesn't it get them confused?" That's the clever bit and the thing which ultimately will lead to banks. The first 12 address bits are called the Row address. The second 12 address bits are called the Column address. When the computer is delivering the Row address it also activates the Row Address Strobe (RAS) wire. When the computer is delivering the Column address it activates the Column Address Strobe (CAS) wire. You may have seen RAS and CAS before when reading about refresh. So, a memory module has RAS and CAS wires in addition to address wires (12 so far) and data wires (8 so far). Now one more thing before we can move on to the joy that is banks. Memory module have the wires listed above, and so do memory chips, except that the memory chips don't have 8 data wires. An 8 bit wide memory chip would be very unusual (well not so unusual in modern DDR2 RAM). Back in the 30 pin SIMM days, each memory chip usually had one (1) data wire. So, to make an eight bit wide SIMM, one installed eight 1 bit wide memory chips. The chips all shared the address and RAS and CAS wires, but each chip had its own data wire. When all those wires left the module, it yielded RAS, CAS, 12 address wires and 8 data wires, one from each memory chip. Later, memory chips with 4 data wires became available. Then it was possible to build 30 pin SIMMs with just two memory chips, which you've probably seen before. After 30 pin SIMMs came 72 pin SIMMs. A 72 pin SIMM still has 12 address wires. So how can they get up to 128MB of capacity? Well, they're wider for one thing. 32 bits wide. So 16M addresses X 32 bits = 16M addresses X 4 bytes = 64MB (2^(12 X 2) X 4 = 64MB). Ooops. We're still short by a factor of two. It would appear that 64MB is the maximum size of a 72 pin SIMM. But we know from experience that it is not. That is where banks come in. A 128MB SIMM is typically made from two banks of 64MB. How is that done? The 72 pin SIMM has four RAS wires. The computer has the ability to activate two of the RAS wires at a time. So, a 128MB SIMM has all the chips that a 64MB SIMM has, and then it has them again. Two sets of chips as if there were two 64MB SIMMs on one board. The first set, or bank, of chips has all of its RAS pins connected to just two of the SIMM RASs. The second set/bank of chips is connected to the other two RAS wires. When the computer wants bank 1, it uses the RAS 1 set of RAS wires. When the computer wants bank 2, it uses the RAS 2 set of RAS wires. If a chip's RAS line never gets used, it will ignore all the addresses and CAS signals and data that the computer is putting on the wires. So, on a two bank SIMM, there are two sets of chips. The chips all share the same twelve address lines. Each chip in a bank shares its data wires with an identical chip in teh other bank. But each bank has its own set of RAS wires, and that's how the computer tells them apart. Of course, this logic which allows distinguishing the RAS wires must be built into the computer. Later 168 pin buffered DIMMs actually have a Bank(0) wire and I'm not exactly sure how that's used, but it's bound to be similar with differences caused by the buffering probably. Now, why would a two bank SIMM work in one computer and not another computer, even though they both support two bank SIMMs (thepickles earlier question)? Because there's more than one way to pair the RAS wires together. If there are RAS wires 1, 2, 3, and 4, and the logic board ties 1 & 3 together as a pair, and 2 & 4 as the second pair, but the SIMM connects 1 & 2 and 3 & 4, then they're wired incompatibly and all the RAS wires are always going to be active on any memory access, and the SIMM will appear as only half the capacity and probably not be very reliable because two chips (ones from each bank) are going to be trying to drive the same data at slightly different times. I've seen this exact problem on the 6100. 128MB SIMMs which work in the Q605 didn't work in the PM6100 because the RAS lines are paired backwards. Now, why do 64MB SIMMs work in the 6100 and not in the 7100/8100/9100? Simple, the 7100, 8100 and 9100 do not support 12 address lines on their SIMMs. They only support 11. So they support 11 + 11 = 22 bits of address => 4M addresses X 4bytes wide => 16MB per SIMM. However, they support two banks, so that's 16M X 2 banks => 32 MB. Yes, 32MB SIMMs are double banked 16MB SIMMs. While the 6100, 7100, 8100 and 9100 all use exactly the same chipset (well slight difference in the 9100 AMIC) the latter three have an additional chip which decodes the address lines from the memory controller to support more SIMM sockets. So the higher address bits are sacrificed to provide support for more SIMMs. The 6100 runs its address lines straight to the SIMM sockets without the intervening logic and it is the only one which supports 12 bit addresses. more thepickle questions: ====================== Is it technically possible to build a 72-pin SIMM with the following specs? a) 2K refresh? faster than 2K refresh? b) 64 or 128MB capacity? (I know this is possible, but bear with me here, please.) c) more than two "banks?" d) Any combination of the above three? ======================= a) Yes, simple. The refresh simply refers to how many row addresses must be worked through during a refresh cycle. Eleven row addresses gives one 2K (2048) addresses. So only memory chips which have 11 address bits in their ROW are 2K. Memory chips which are 12 X have 4K row addresses and memory chips with 10 address bits have 1K (1024) row addresses. Since the memory controller usually refreshes rows at a fixed pace, a memory chip with more row addresses needs to be able to tolerate a longer period between refreshes. b) Yes, as you know c) Possibly. I've never seen one, but there are four RAS lines. In theory, it should be possible to build a four bank 72 pin SIMM. The maximum memory per bank is still controlled by the address bits (12) and the width (4 bytes) so banks cannot have more than 64MB each. d) If you have a 64MB or 128MB SIMM then you have 4K refresh because you have 12 row address bits. In theory, one could have a two bank 64MB SIMM built out of 11 X 12 (row X column) parts, but as far as I've seen, the row address is never shorter than teh column address, so I do not think anyone ever made 11 X 12 memory chips. Finally, your 64MB two bank SIMM. That would have to be 12 X 11 X 2. That is 12 row bits X 11 column bits, by 2 banks. You would need a machine with a memory controller which is capable of addressing 12 X 11 chips. Most of them can't. They do 12 X 12 (if you're lucky) and 12 X 10 and 11 X 11, but 12 X 11 is rare. You might try it in the Q605/LC475. -----------end of response --------------------