List of Altair/IMSAI S100 signals Copyright 1999 Herb Johnson, updated June 1999, again July 2006 Notes: Pins are numbered 1 (leftmost) through 50 (rightmost) on the component side: pins 51 (rightmost) through 100 (leftmost) on the circuit trace side. Column "dir" is signal direction relative to the processor or front panel, depending on signal "type". I suggest you view or print this list with a monospaced font. *'ed signals are rarely used or troublesome lines on S-100 systems subsequent to the original IMSAI/Altair systems. /'ed signals are active when they are LOW, not HIGH. ()'ed signal names are on IMSAI only; []'ed on Altair only. The Altair 8800b may not use or support some Altair bus signals. note 1; Pin 60 on Altair was a write protect signal from front panel. On IMSAI it was a front panel input. See my S-100 home page for a link to a document about pin 20 and pin 60 for details. Altair/IMSAI S100 signals ------------------------- pin signal type dir function 01 +8V power +8 volts 02 +18V power +18 volts 03 XRDY fr panel out external ready to processor 04 VI0 control in vector interrupt line 0 05 VI1 control in vector interrupt line 1 06 VI2 control in vector interrupt line 2 07 VI3 control in vector interrupt line 3 08 VI4 control in vector interrupt line 4 09 VI5 control in vector interrupt line 5 10 VI6 control in vector interrupt line 6 11 VI7 control in vector interrupt line 7 12* XRDY2(NMI) control in 2nd external ready OR Z80 interrupt 13 14 15 16 17 18 /STADSB control in disable processor status lines 19 /CCDSB control in disable processor control lines 20 [UNPROT](GND) fr panel in unprotect memory 21 SS fr panel out single step processor 22 /ADDDSB control in disable processor address lines 23 /DODSB control in disable processor data out lines 24 PHASE2 clock out primary processor clock line 25* PHASE1 clock out "inversion" of PHASE 2 processor clock line 26 PHLDA control out processor in HOLD condition 27 PWAIT control out processor in WAIT condition 28 PINTE control out processor permits interrupts when active 29 A05 address out address line 5 30 A04 address out address line 4 31 A03 address out address line 3 32 A15 address out address line 15 33 A12 address out address line 12 34 A09 address out address line 9 35 DO1 data out data output line 1 36 DO0 data out data output line 0 37 A10 address out address line 10 38 DO4 data out data output line 4 39 DO5 data out data output line 5 40 DO6 data out data output line 6 41 DI2 data in data input line 2 42 DI3 data in data input line 3 43 DI7 data in data input line 7 44 SM1 state out processor instruction fetch signal 45 SOUT state out processor I/O write signal 46 SINP state out processor I/O read signal 47 SMEMR state out processor memory read signal 48 SHLTA state out processor HALTed signal 49* /CLOCK clock out 2MHz clock signal 50 GND power logical and power ground Altair/IMSAI S100 signals (cont.) --------------------------------- pin signal type dir function 51 +8V power +8 Volts 52 -18V power -18 Volts 53* /SSWDSB fr panel out sense switch disable (of data inputs) 54* /EXTCLR fr panel out clear (reset) I/O devices on bus 55 [RTC] ??? ??? real time clock (Altair) 56 /STSTB control out processor status strobe signal 57 [DIG1] fr panel out data input gate 1 (Altair) 58 [FRDY] fr panel ??? Front Panel Ready (Altair) 59 60 [PROT](T5) fr panel ??? see note 1 61 62 63 64 65 (/MREQ) control out Z80 memory request 66 (/REFRESH) control out Z80 processor DRAM refresh 67 68* MWRT ctrl/frp out memory write from processor or front panel 69 /PS control in write-protect status of current memory board 70* [PROT](GND) fr panel out input to write-protect status of memory board 71* RUN fr panel out stops processor 72 PRDY control in controls run/WAIT state of processor 73 /PINT control in request for interrupt to processor 74 /PHOLD control in request for HOLD to processor 75 /PRESET control in forces processor to reset state 76* PSYNC control out marks beginning of each processor cycle 77 /PWR control out active when processor writes (I/O or memory) 78 PDBIN control out active when processor reads (I/O or memory) 79 A00 address out address line 0 80 A01 address out address line 1 81 A02 address out address line 2 82 A06 address out address line 6 83 A07 address out address line 7 84 A08 address out address line 8 85 A13 address out address line 13 86 A14 address out address line 14 87 A11 address out address line 11 88 DO2 data out data output line 2 89 DO3 data out data output line 3 90 DO7 data out data output line 7 91 DI4 data in data input line 4 92 DI5 data in data input line 5 93 DI6 data in data input line 6 94 DI1 data in data input line 1 95 DI0 data in data input line 0 96 SINTA control out acknowledge signal for PINT request 97 /SWO control out processor in write status 98* SSTACK control out processor in stack read/write status 99 /POC ft panel out power-on clear signal 100 GROUND power and signal ground